Consider the IP Catalog, mainly the Clocking Wizard. For this component we can stablish an input clock of 12MHz, as the boards has, and the output is multipled by power of two values.
This allow a power up in the clock speed, consequently, the PWM could be faster according the needs. Unfortunately, my implementation of HACK CPU is not efficient and there is a timming violation with superior clock frequencies. To test this I only changed the clock input for each instance and the intructions are the same from the last blog.
The first step is a Clock Wizard IP instantiation,
DIV: ENTITY WORK.clk_wiz_0
port map(
CLK16 => CLK16,
CLK8 => CLK8,
CLK4 => CLK4,
CLK2 => CLK2,
CLK1 => CLK1,
reset => RST,
clk_in1 => CLK_SYS
);
Here, the block is syncrhonized with the system reset and the clock input of the module is assigned with the 12MHz board clock. In the output we have a set of multipled clocks by 1, 2, 4 and so on. This allow modify the clock base of the PWM modules.
PWMA: entity work.WG_PH
generic map( Width => 16
)
port map( CLK => CLK8,
MAX => pwmMaxA,
CMP => pwmCmpA,
Q => LEDS(2)
);
PWMB: entity work.WG_PH
generic map( Width => 16
)
port map( CLK => CLK4,
MAX => pwmMaxB,
CMP => pwmCmpB,
Q => LEDS(1)
);
PWMC: entity work.WG_PH
generic map( Width => 16
)
port map( CLK => CLK2,
MAX => pwmMaxC,
CMP => pwmCmpC,
Q => LEDS(0)
);
As the code above shown, each instance of the PWM module has a 16 bit width to accomplish the processor word length. Remember the ISA of the HACK CPU, the processor has 15 bits of mantissa and one bit of sign. The three instances has the same structure but different memory map and clock source. These allow the PWM frequency configuration using software for the frequency and ducty cycle configuration, and hardware for the clock base module input configuration. Hence, the module C is faster than module B, and module B is faster than module A.
You can see the Duty Cycles of each PWM module is the same of the las blog, but the clock base of the modules allows a different PWM frequency even the same instructions. A benefit of the IP Catalog is the quick implementation of modules like Counters, Memories, Transforms and more. Another example is the ROM memory with the Block Memory Generator. This wizard allow the an initilization file. Each time we generate our .hack file with the courseware tools it is possible to create a .coe file with the code. The following represent the .coe file for the configuration of the PWM modules. You only need replace the memory_initialization_vector with the respective compiled code.
;****************************************************************** ;******** Example of .COE file ********* ;****************************************************************** ; ; This .COE file specifies initialization values for PWM modules ; configuration with HACK CPU. The wizard uses this information to ; instantiate the ROM memory with the instructions memory_initialization_radix=2; memory_initialization_vector= 0000010000000000 1110110000010000 0100000000000011 1110001100001000 0000000010000000 1110110000010000 0100000000000100 1110001100001000 0000010000000000 1110110000010000 0100000000000101 1110001100001000 0000001000000000 1110110000010000 0100000000000110 1110001100001000 0000010000000000 1110110000010000 0100000000000111 1110001100001000 0000001100000000 1110110000010000 0100000000001000 1110001100001000 0000000000011001 1110101010000111;
The next step, create a software functionality for the PWM clock base configuration. The memory map should be updated to accomplish a peripheral philosophy in a microcontroller.
