1. Brief
In previous blog, SHA256 has been elastrated and acomplished in software core and hardware core.
Only with independant port, can sha256 accelerator runs. There have been choice of SPI, I2C, USB or UART. Fully understand of protocle is important and UART is simplest one.
2. UART in FPGA
There are UARTlite IP or customized synthesis.
The uart input and output is ,
similarly, the simple uart can be done in verilog as attached uart.v.
3. Create new project and add verilog file top.v, uart.v and sha256_hash_hw.v as in attached zip file.
top.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/01/28 14:55:06
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input clk,
inout uart_tx,
inout uart_rx,
output led
//input btn_in
);
//not(led,btn_in);
//wire [0:0] ledon ;initial begin ledon = 1'b0; led=ledon; end
wire clk,tx,rx;
//reg in,out;
wire [0:31] in =32'h428a2f98 ;
wire [0:255] out;
assign led = 1'b0;
wire reset = 1;
reg start, send;
wire busy;
uart hashin(
.uart_clk(clk),
.uart_rx(rx),
.uart_tx(tx)
);
sha256_hash_hw hash(
.IN(in),
.OUT(out)
);
uart_tx tx(.clk(clk), .tx(uart_tx), .send(send), .data(out[0:7]), .busy(busy));
uart_rx rx(.clk(clk), .rx(uart_rx), .ready(ready), .data(in));
endmodule
4. Revise constrain file and open led, clk, uart_rx, uart_tx ports, as shown in variants in top.v
5. Then run synthesis and implementation,
Synthesis passed and run implementation then
Implementation passed and generated bitstream
Bitstream is generated and open hardware manager.
In hardware management, press autoconnect hardware,
Program the device with bitstream file in .bin format
Then write bitstream complete, the code can work.
6. Summary
Within relatively short period, I have tried hardware accelerator and softcore accelerator in microblaze IP. Basic function is approved and passed the validation.
Further development on timing, clocking and bit-transition, there is one part not accomplished, IP packaging, Packing the verilog project into customized IP. It is prefererable in AXI porting, to be integrated into microblaze softcore. Fully enhance the function and flexiblilty of the Hardware Acceleration.
For further development, simulation can be very good helper as below. There is not enough time showing how the simulation works, but that function is fairly easy to use and not explained here.
