FPGA MIDI Music Synthesizer -- Episode 388

Hi Andy, 

Instead of using separate might for single cycle wavetable can't we read through multiwave as well?. It would be helpful to know in that case whether we could read or cycle through multiwave format wavetable sample using rotary encoder to interpolate between them. 

Excellent project

You can message me here in the community, but I suspect there are people here that are far more knowledgeable. If I remember correctly, this was only my second or third project using an FPGA. You can always ask specific questions in the FPGA Group.

I suspect the answer to this is "yes", but I don't know for sure without actually attempting it. I haven't had much time for FPGAs since I did this project.

Do you think that would be possible to implement poliphony as well as an external cv input using the same board?

Would be possible to drive an external adc?

This project is really making me see light after a long tunnel, and guess will do also for the many who see fpga programming unreachable,

very well explained. Hope you can give me some hint to go on in my project. How could i get in touch with you?

Just out of curiosity, has anyone else here tried actually putting this together? I did, and it didn't work right out the box for me.

When I looked through a logic analyzer, it seemed like the bits were being read from the Rx line consistently a few hundred clock cycles too early. It may have something to do with the fact that I'm generating my MIDI signal from DAW software via a FireFace800 (old firewire sound interface from 20 years ago). When I looked at the generated Rx through the LA, the bit period was...not exactly predictable. It should change bits every 32 us, but mine seems to vary by like +/- 3-4 us. Anyways, when I looked at the code in MidiByteReader.v, it seemed like it was trying to read the bits exactly every 1600 20ns clock cycles (+ the 10 clock cycle "debounce") which would mean it's trying to read bits right around the bit boundaries of the signal. So, I changed the "debounce" holdoff to 800 clock cycles, so that now it tries to read bits exactly in the middle between two bit boundaries instead, and...voila, it worked!

I was just curious if anyone else had the same issue that I did or not.

did you guys checked this out? A subtractive music synth fully implemented in FPGA

Man, I really gotta dig into FPGAs soon! So many groovy things you can do with them!

I literally just made a project that is very similar to this. It takes the MIDI and drives 32 stepper motors to play music.

It was also deigned for the DE0-nano and I fully documented the project and have my Verilog (and PCB designs) there too.

It is here: https://sites.google.com/a/vt.edu/amp_lab/projects/stepper-synth-v2

It was fully funded by my university too!