The Vivado Design suite supports 7-Series, Zynq, and UltraScale programmable families. It is developed to address the productivity bottlenecks in system-level design, integration, and implementation. The Vivado Design suite provides ease-of-use, system level integration capabilities, and new tools and methodologies, increasing overall productivity.
To participate download Vivado 2020.1 and the attached lab book below! You can also download the lab book here!
The Vivado Design Suite from Xilinx offers tools and methodologies to speed up FPGA development, while improving productivity. Within Vivado, developers can leverage C-based design, capture, simulate and implement programmable logic designs targeting Xilinx FPGA and SoCs (System-on-Chips). This three-session introduction to Xilinx Vivado Design Suite will examine how we capture designs in Vivado using both RTL entry and IP Integrator. Following design capture we will examine Vivado’s simulation capabilities that help ensure the performance of the captured design aligns with requirements. When we reach the desired functional performance level, we will move on to design implementation and programming file creation for deployment. Just as with real life, our journey does not end there. We will also explore how we can debug the implemented design on the device as it is integrated into the wider system, should the need occur.
Session 1:
This session will consist of an overview and introduction to Vivado. You will learn key element of FPGA design, learn about the different views inside Vivado, and explore what they can be used for.
In this session we will get an overview and introduction to Vivado, key elements of FPGA design, and the different views inside Vivado and what they can be used for.
Topics covered include: •
- FPGA flow – RTL -> Synthesis -> Place and Route -> Bitstream •
- What do we use Vivado for? What is its role in FPGA and SoC Development?
- Design entry in Vivado -> RTL View
- Simulation -> XSIM (Vivado RTL Simulation)
- Implementation Flow -> Synthesis View, Implementation, Bit Stream
Dates and Register for Free:
Presenter:
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| Founder and Lead Engineer, Adiuvo Engineering & Training Ltd |
| Adam has over 18 years engineering experience of which a significant number of these are at Design Authority / Responsible Engineer level on complex System and Electronic projects for advanced satellite payloads, safety critical systems (SIL4) and other high performance systems. He is both a Chartered Engineer and Fellow of the IET, as well as, a prolific blogger on technical subjects such as Electronics design, FPGA design and Reliable techniques.He is also the author of the MicroZed Chronicles, a weekly blog which focuses on the Xilinx Zynq & Zynq UltraScale+ SoC, as well as, the Vivado and SDSoC tool sets. The series contains over 250 in depth technical articles, providing examples and how to's which cover every aspect of using the device from basics to advanced concepts such as Asymmetric Multi Processing and High Level Synthesis. |
 | Working_With_Vivado_P1.pdf |
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