Simple analog JFET switch - part 2: linear range and limitations

I reviewed an analog small signal switch in post 1: Simple analog JFET switch - part 1: schema, simulate and test. Here I'm checking what the limits are - the small linear part of the operational region where the P-channel JFET acts as a resistor. The circuit is published on neatcircuits.com

JFETs are linear for small signals. The schema here is for a consumer audio signal level, and that signal fits in that range for the J176 that I'm using.

source: wikipedia

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Simple analog JFET switch - part 2: linear range and limitations

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source: w2aew youtube channel

The device, in the DC stable state (bias condition), has source and drain virtually at ground level.

The gate is also almost at ground level, just a diode drop (D1) above ground.

I've simulated this by using LTspice DC operating point analysis.

This time, the resistors are all 3 47K ones.

The biggest difference between the simulation and my bench measurement is the diode drop I measure is 530 mV, not the 509 mV that LTspice gives.

image: DC operating point simulation (steady state)

A P-chanel JFET where the gate is just 0.5 V above source, is conducting.

In the image below, I've indicated what VGS curve this design is operating in when the switch is on:

source: annotated ON Semiconductor datasheet for J176

When testing the design, it all works well, with an input signal of up to 1.6 Vpp.

In the capture below,

• the yellow trace is a 3 kHz, 1.58 Vpp input signal measured on the drain pin. You can't see it because it's under the output signal, that perfectly matches.
• the light blue signal is the output of the JFET, measured on the source pin. Perfectly matching (and hiding) the input.
• the magenta line is the gate. Held at 0.5 V
• the dark blue line is VGS. Measured with a differential probe because both points are not ground.

image: oscilloscope capture just before Gate-Source Cutt-off starts

But when the amplitude of the input rises (I've put the dashed cursor B at the level where the effect becomes obvious), the source no longer follows the drain.

What's happening?

image: oscilloscope capture when Gate-Source Cutt-off is crossed

To see that, check the dark blue VGS signal.

At a certain point (I put full-line cursor A there), VGS reaches the Gate-Source Cutt-Off voltage (VGS(off)).

According to the data sheet this is between 1 and 4 V for the J176.

For my transistor, it happens to be around 1.3 V.

VGS is the diode drop - VG. So that gives us an AC leeway of 1.3 V - 0.5 V = 0.8 V on the negative side.

An AC signal with 1.6 Vpp is just manageable with my JFET.

Increasing the supply voltage will not help, because the diode drop is the deciding factor here, and it's reasonably flat when using large pull-up resistor that draw only small current.

source: ON Semiconductor datasheet for J176

The effect on the output is pertinent. Once the signal pushes the source low (and as such increases the positive voltage between source and gate), you get closer to that cut-off point.

One it's reached, the FET stops being the linear resistor it was and the output gets strongly attenuated.

It's some kind of self-balancing system because the further above the cut-off, the stronger the effect.

This will render the negative part of the sinus input signal into a flattened, lob-style curve, while the positive half is still good.

Here is LTspice's take on this situation:

image: LTspice simulation, taken at input and output before and after the decoupling capacitors

The output is slightly attenuated vs the input in LTSpice because I measured before the input cap and after the output.

I can easily change that, but maybe this can be an exercise for you? The model is attached to post #1.

Given this effect, and taking worst case (VGS(off) = 1 V), we are still safe for a consumer product's line signal.

To handle professional audio line levels, you should consider  a J175 or another JFET with a higher VGS(off).