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  • Author Author: Jan Cumps
  • Date Created: 14 Jul 2018 12:44 PM Date Created
  • Views 2368 views
  • Likes 11 likes
  • Comments 8 comments
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DAC8775 Quad-Channel DAC EVM - unlicensed roadtest part 1: Raw SPI

Jan Cumps
Jan Cumps
14 Jul 2018

A year ago, the DAC8775 was the subject of the Quad-Channel, Analog Output Module RoadTest.

My element14 friend DAB was not impressed by the EVM and its software. I asked if he wanted to trade the board for another evaluation module, and he did. After some hick-ups with post services, the evaluation kit for the DAC is finally in my hands.

image

My review will be different than the official reviews, because I don't have the device to connect the EVM to USB. I will use SPI to talk to the device instead of the kit's GUI.

Maybe this will help future designers to control the device. There are very few code examples available.

 

Click here for my failed attempt with a Bus Pirate as SPI master. I'm doing everything over again in this blog with a Hercules microcontroller. I know the SPI module better on that family.

 

 

Test Setup

 

I'm using a TI Hercules Safety microcontroller to generate the SPI traffic.

My logic analyser is a Papilio Pro FPGA dev board.

image

The Hercules controls SPI, drives the nRESET pin and reads the nALERT pin of the DAC. The logic analyser probes each of these signals.

 

SPI Communication Test

 

The DAC has a test mode where you can validate if the communication works. A rather nice feature. It helped me getting the control of that device stable.

The IC has two user bits in different registers. If you set that bit in one register, it's mirrored in a bit in that other register.

This allows you to verify the full write -> read cycle. First write the value, then send a read request and validate the returned bit.

 

image

The bit to set is the LSB of register 0x02.  It's false by default.

If you set it true, the 7th LSB of register 0x0b is set. If you manage to read that register from your firmware and the bit is true, you know you've mastered both write and read process.

In the code below, I'm setting the 0x02 bit in section 1. Then I ask the DAC to return the value of 0x0b in section 2, and read the results in section 3.

 

    // toggle user bit
    TX_Data_Master[0] = 0x02;
    TX_Data_Master[1] = 0x00;
    TX_Data_Master[2] = 0x01;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    // read user bit
    TX_Data_Master[0] = 0x8b;
    TX_Data_Master[1] = 0x00;
    TX_Data_Master[2] = 0x00;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    // nop should return user bit
    TX_Data_Master[0] = 0x00;
    TX_Data_Master[1] = 0x00;
    TX_Data_Master[2] = 0x00;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

 

The technical spec describes both the write and read process.

Long story short:

  • write cycle is 8 bit register address then 16 bits of value. It is effective (conditions apply image) at the end of the conversation when the nCS is switching high.
  • read cycle is 8 bit register address with MSB set high + 16 bits of random, then a nop (3 times* 0x00) to clock in the response.

The technical spec does a better attempt to explain this (although that one is difficult to understand too if you're a first time user of that DAC).

Comment below if you want to elaborate on the protocol.

image

In the picture above, you see this scenario reflected.

  • The first block of 3 bytes sets the user bit in register 0x02 (check the MOSI line).
  • The second bloc requests the value of 0x0b (0x8B because the MSB is set high for reading - check MOSI again).
  • The third block shows that while we are sending the 3 NOP bytes (MOSI), the DAC uses these clock cycles to send the content of 0x0b (MISO line).

note: any MISO values appearing when you're not using a read command are to be ignored in this scenario. Read the spec's daisy chain section to learn why that data is there.

 

Setup Steps

 

The technical spec of the DAC8775 describes the process to set up the DAC. Like most programmable devices you work with a set of registers.

image

source: technical spec of DAC8775

 

In my firmware, I've swapped the first 2 and the second 2 blocks. I used pseudo code from a support article online and they configured the DAC registers first and the Buck-Boost second.

It's not a good practice though, because after step 0x04 you get a non-desired output. Keep the order of the diagram above.

 

    //
    TX_Data_Master[0] = 0x03;
    TX_Data_Master[1] = 0x00;
    TX_Data_Master[2] = 0xf0;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    //
    TX_Data_Master[0] = 0x04;
    TX_Data_Master[1] = 0x10;
    TX_Data_Master[2] = 0x00;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    //
    TX_Data_Master[0] = 0x06;
    TX_Data_Master[1] = 0x00;
    TX_Data_Master[2] = 0x0f;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    //
    TX_Data_Master[0] = 0x07;
    TX_Data_Master[1] = 0x06;
    TX_Data_Master[2] = 0x1f;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

    //
    TX_Data_Master[0] = 0x05;
    TX_Data_Master[1] = 0xff;
    TX_Data_Master[2] = 0xff;
    /* Initiate SPI3 Transmit and Receive through Polling Mode */
    spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

 

The result is that the value written to register 0x05 is reflected at the DAC output (we've selected output A in this example).

And it does image.

 

image

 

Complete SPI Communication

 

The whole setup involves some pre-steps. You have to drive the nRESET pin low for at least 10ns, and for good measure, I also send a software reset (0x01 0x00 0x01).

This is the capture of my logic analyser.

image

Easter egg: the annotations in the picture above are not correct. If you want the right ones, comment below.

 

Related Blog
DAC8775 Quad-Channel DAC EVM - unlicensed roadtest part 1: Raw SPI
DAC8775 Quad-Channel DAC EVM - part 2: Firmware
DAC8775 Quad-Channel DAC EVM - part 3: Slew Rate Control
DAC8775 Quad-Channel DAC EVM - part 4: Current Mode
DAC8775 Quad-Channel DAC EVM - part 5: HART Interface
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Top Comments

  • DAB
    DAB over 7 years ago in reply to rachaelp +4
    Hi Rachael, Yes, in my day, these devices were much more simple, but much more limited. I appreciate the flexibility of SPI control devices, but they do add another level of complexity. With my disability…
  • DAB
    DAB over 7 years ago +3
    Nice post Jan. Now you can appreciate how difficult I found the board to use. I like simple user interfaces, not a drawn out complicated multistep process just to get an output. DAB
  • Jan Cumps
    Jan Cumps over 7 years ago +3
    Here's a measurement of default rise time, with the output set to 0 -> 5V and fully driven: The slew rate can be programmed. I'll try to set it and measure the result ...
  • DAB
    DAB over 7 years ago in reply to rachaelp

    Hi Rachael,

     

    Yes, in my day, these devices were much more simple, but much more limited.

    I appreciate the flexibility of SPI control devices, but they do add another level of complexity.

    With my disability it is not easy for me to dive into this level of complexity, so I will try to find simpler solutions.

     

    DAB

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  • rachaelp
    rachaelp over 7 years ago in reply to DAB

    DAB  wrote:

     

    Now you can appreciate how difficult I found the board to use.

    I like simple user interfaces, not a drawn out complicated multistep process just to get an output.

     

    I've designed in a lot of ADC's and DAC's in products over the last few years, they all have an SPI interface to an MCU for setup/control. I guess that's the downside of modern devices which integrate much more functionality into them. Some of the complexity of the design gets pushed into the software required to control them so if you aren't expecting that or don't have an easy way to implement the software required to configure them you're a little stuck!

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  • Jan Cumps
    Jan Cumps over 7 years ago

    For the interested: slew rate control of the DAC8775: DAC8775 Quad-Channel DAC EVM - part 3: Slew Rate Control

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  • Jan Cumps
    Jan Cumps over 7 years ago

    firmware explanation: DAC8775 Quad-Channel DAC EVM - part 2: Firmware

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  • Jan Cumps
    Jan Cumps over 7 years ago in reply to Jan Cumps

    Here's an example of slew rate of slew rate update frequency of 131,145 Hz, single bit step.

    image

     

    Code change to achieve that:

     

        TX_Data_Master[0] = 0x04;
    //    TX_Data_Master[1] = 0x10; // output on, default slew rate
        TX_Data_Master[1] = 0x13;  // output on, slew rate 131,145 Hz
    //    TX_Data_Master[2] = 0x00; // slew rate off
        TX_Data_Master[2] = 0x10; // slew rate on, step: LSB
        /* Initiate SPI3 Transmit and Receive through Polling Mode */
        spiTransmitAndReceiveData(spiREG3, &dataconfig1_t, 3, TX_Data_Master, RX_Data_Master);

     

    Naive calculation of theoretical rise time:

     

    freq (Hz)time (s) / step1311457,62514773723741E-06Number of steps (80% of 0xff)rise time524280,399771245567883

     

    note: for above two measurements, I loaded the DAC with a 330R resistor. It's on a breadboard, so there will be parasitic capacitance.

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