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  • Author Author: Jan Cumps
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Hercules LaunchPad and GaN FETs - Part 2: Make a BoosterPack

Jan Cumps

I'm designing a BoosterPack to evaluate GaN devices with the help of a microcontroller.

 

             image

 

The kit will have a GaN half-bridge that can control an output of 20V and 10A.

Currently the prototype can control switching frequency and duty cycle.

I'm also planning a stretch goal to integrate the design with LabView. You can then use this as a part of a test setup.

 

 

 

The Design Exists

 

I have a working prototype. I modded an existing LMG5200 evaluation kit a while ago.

I removed the discrete PWM generator and replaced it with microcontroller managed signals.

image

 

This proof of concept works, both electronics and firmware. I can make a more sturdy version now.

The switching layout is fully based on the design guidelines and the evaluation kit's PCB.

Because of the high switching frequencies and high currents, that part of the design is critical.

I'm trying to place all components similar to the application notes. This will be my first 4-layer PCB design.

 

Status

 

I have the schematic ready.

I had to create a few components and footprints (both for LMG5200 and rotary encoder, footprint only for the inductor).

image

For the PCB, I have a provisional layout. I haven't routed a single trace yet.

But I have uploaded that intermediate status to OSHPark to get an idea of how this device will look like.

Before doing that routing, I first have to verify if I can source all the components that I'm planning to use.

In particular the SMD 360° rotary encoder may be a tricky purchase.

 

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To be continued...

 

Related Blogs
Hercules LaunchPad and GaN FETs - Part 1: Control Big Power with a Flimsy Mouse Scroll Wheel
Hercules LaunchPad and GaN FETs - Part 2: Make a BoosterPack
Hercules LaunchPad and GaN FETs - Part 3a: BoosterPack Layout - Reference Design
Hercules LaunchPad and GaN FETs - Part 3b: BoosterPack Layout - my version
Hercules LaunchPad and GaN FETs - Side Note A: BoosterPack Layout - Custom KiCad Parts
Hercules LaunchPad and GaN FETs - Side Note B: Look at the PCB
Rotary Encoders - Part 1: Electronics
Checking Out GaN Half-Bridge Power Stage: Texas Instruments LMG5200 - Part 1: Preview
Rotary Encoders - Part 4: Capturing Input on a Texas Instruments Hercules LaunchPad with eQEP
Vintage Turntable repair: Can I fix a Perpetuum Ebner from 1958 - part 4 - Hercules LaunchPad Enhanced PWM try-out
Parents

  • A PCB! And it's a Boosterpack (whatever that is)!

     

    I don't know what you intend for the tracking (please don't say it's going to be a job for an autorouter, entertaining though that might be), but wouldn't it work better if you rotated P3 (the output connector) by 180 degrees. It would then allow you to have the power ground (input gnd - GaN - output gnd) as copper on the top layer. Since all the power tracking could then be copper on the top, you might consider whether it would work well enough as a 2-layer board.

  • in reply to jc2048

    I'm using the layout advice in  the 'Layout Considerations for LMG5200 GaN Power Stage' appnote from the manufacturer.

    They have a proposal for a double layer pcb in the datasheet with this remark:

    To maximize the efficiency benefits of fast switching, its extremely important to optimize the board layout such

    that the power loop impedance is minimum. When using a multilayer board (more than 2 layers), power loop

    parasitic impedance is minimized by having the return path to the input capacitor (between VIN and PGND) small

    and directly underneath the first layer

     

    [...]

     

    Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance.

    However, if design considerations allow only two board layers, place the input decoupling capacitors immediately

    behind the device on the back-side of the board to minimize loop inductance.

     

     

    Four layer layout:

    image

     

    Two layer layout:

     

    image

  • in reply to Jan Cumps

    But both of those cases assume the power ground is on a lower layer. In that case the four-layer solution IS better than the two layer solution. But if you can have the power ground on the top, you don't need any vias and that's even better, isn't it?

  • in reply to jc2048

    In the 4 layer configuration, that lower layer is just underneath the device, in the top-middle layer.

    In the two layer layout, the full PCB thickness is between the two.

    I'm going for the 4-layer option now (I'm no hero, am I?) and try to get that as close as possible to the appnote advice.

    If that works out OK, I can make make a second one with two layer, and have something to compare against.

     

    I'm not using the autorouter; I'm not even using normal traces for most of this board, but flood filled planes all over.

    I have example Gerbers of the appnote's PCB that I can learn from.

    Only the input part and the rotary encoder block will be normal traces.

Comment
  • in reply to jc2048

    In the 4 layer configuration, that lower layer is just underneath the device, in the top-middle layer.

    In the two layer layout, the full PCB thickness is between the two.

    I'm going for the 4-layer option now (I'm no hero, am I?) and try to get that as close as possible to the appnote advice.

    If that works out OK, I can make make a second one with two layer, and have something to compare against.

     

    I'm not using the autorouter; I'm not even using normal traces for most of this board, but flood filled planes all over.

    I have example Gerbers of the appnote's PCB that I can learn from.

    Only the input part and the rotary encoder block will be normal traces.

Children
  • in reply to Jan Cumps

    Right. I've read the datasheet. Should have done that first. How many times in my life have I said "Don't guess - read the datasheet"?

     

    Firstly, I'm not an expert. I don't have direct experience of switching power at these sort of edge rates. So I'm someone who is interested and trying

    to understand. I'm certainly not telling you what to do.

     

    Two. TI have decades of experience and can hire the best, so I'm not questioning them at all.

     

    Three. They've done it and it works, so follow their guidelines. If it works for them, it'll work for you. [And they must have test equipment that's

    orders of magnitude better than anything you or I have, so they've actually seen it working and can measure it properly.]

     

    Having said all that, I still don't entirely follow why they've chosen the layout that they have.

     

    My initial reaction would have been something like this:

     

     

    image

     

    That minimises the loops, keeps the inductance low, and avoids vias which look horrible when you get up to frequencies of more than a few hundred

    megahertz. Having the same copper layout on all layers and stitching them together with vias would help a bit further, though it doesn't reduce the inductances by a

    factor of four because the vias look so nasty. My layout does limit the number of capacitors a bit and you desparately need the paralleling to reduce

    the effect of the lead inductances and stand any sort of chance of getting charge to the GAN in time. Think I need to think about this a bit more. Perhaps it's

    a job for Simulator Man!

     

    BTW I was joking about the autorouter (in the light of another thread where the poster is trying to control an autorouter by shuffling components

    around and Rachel and the Three Eagleteers are (still) valiently trying to save the day). I knew that you knew what you're doing and would use copper.

    Trouble with jokes is they tend to get stuck in the customs area at national boundaries and not travel well.

  • in reply to jc2048

    I'm starting the routing. First step: layout of the power planes of the bottom layer.

    image

  • in reply to jc2048

    image

     

    The thermal reliefs on the power pads will go when I'm switching from coarse layout to fine routing. I'll also improve clearance then.

    At the moment it's handy to have the reliefs because it makes the pads visible inside the fill areas.

  • in reply to Jan Cumps

    Bottom and lower middle layer routed:

     

    image

  • in reply to Jan Cumps

    First routing phase finished.

    All components connected.

    4 layers have all planes, vias and traces that are needed

    need to resolve 'flood areas too close' warnings

     

    {gallery} First Routing Phase

    image

    3D view front

    image

    3D view back