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  • Author Author: Jan Cumps
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Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA

Jan Cumps

The Papilio FPGA board is an excellent FPGA development board. It's got a Xilinx Spartan chip.

And you can use it as a quite capable logic analyzer.

That's no surprise. The developer of the Papilio, Jack Gasset from Gadget Factory, was also involved in the design of the Dangerous Prototypes Open Workbench Logic Sniffer.

Just compare the schematics, and you'll find more similarities than differences.

In essence, the Logic Sniffer is a Papilio with a Logic Analyzer design loaded, and with input buffering.

What we 'll do here is: load that same code (it's open source) to the Papilio,

That alone is enough to get a logic analyzer that can sample 32 channels at 200 MHz.

I'll also look at a level translator. That's a small 4-component circuit that allows to measure 5V digital signals.

 

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Hardware

 

The bare minimum to start is one of the Papilio boards and a computer with USB port that can run Java.

With that alone you can start probing 3.3 V digital signals. So don't connect it directly to your Arduino UNO. The Arduino's signals are 5 V and the Xilinx Spartan doesn't like that.

I am using a Papilio Pro with a Xilinx Spartan 6LX FPGA. There's also a port available for the Papilio One with a Spartan 3E.

 

 

If you want to probe 5V signals, you'll need a level translator. Gadget Factory has a few buffer wings (the Papilio lingo for shield).

The Gadget Factory wing designs are open source. I've made my own based on their design. More on that later.

 

Firmware

 

I believe that firmware is not the right name for that thing you load to an FPGA. The best other description I have found is bitstream. Whatever.

The sources are available on this thread on the Gadget Factory forum. They are no longer available. I attached my project as a ZIP to this post.

You'll need the Xilinx ISE Design Suite to create the binary file.

 

tip: I have loaded the logic analyzer bitfile to Flash, so that it's always available at power-on.

When I'm using the Papilio as FPGA development board, most of the times I load my designs to the FPGA directly and leave the LA design alone. After a power cycle or reset, it's an LA again.

 

Client software

 

I'm just going to point to my previous blog post here. It's exactly the same: Make a Logic Analyzer from your Dev Kit Part 1: Arduino UNO

 

Using the Papilio as Logic Analyzer

 

This video here walks through an i2c analysis:

 

 

There are a few steps to do to be able to start samping:

Check your COM port:

When you plug in your analyzer, your computer will have two new COM ports. The port you need to select is the one with the highest number.



Connect your signals to the logic analyzer. For my i2c probing, I've connected ground to ground, SCL to A0 and SDA to A1

Then set up the sampling:

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With the above settings, we'll sample at 200 MHz, triggering on a low of the i2c clock.

Here's the resulting sampling signal view:

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Once you're at this stage, you can use the i2c protocol analyzer to view the data and annotate your signal.

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Just for kicks I'm also showing the Xilinx ISE. I haven't written any of the verilog (I'm only capable of writing some basic VHDL).

 

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Related Blog
Make a Logic Analyzer from your Dev Kit Part 1: Arduino UNO
Make a Logic Analyzer from your Dev Kit Part 2: Papilio FPGA
Make a Logic Analyzer from your Dev Kit Part 3: Level Translator and Buffer
Attachments:
Papilio_Pro_OLS.zip
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