I want to improve my skills on FPGA design so I decided to cover Verilog/System Verilog from scratch. I believe one of the best methods of learning is teaching, therefore, I will have a diary of my progress. Hopefully, it will help other community members too.
What I have planned to do is start from the very beginning of Verilog to go deep topics as long as I go. Not only cover the syntax of the language but also mention digital design methods I need to implement that subject and FPGA implementation of the task. I know it is very time-consuming and there will be always something prevents me to write but I will do my best to write weekly posts.
I will be using Verilog HDL - A Guide to Digital Design and Synthesis written by Samir Palnitkar. I will be happy if you suggest books you like so learners can buy them.
You can follow all the articles related to my verilog diary by searching my_verilog_diary or coming to this post. I will update this post if there is an update.