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Unspecified / Undocumented PINs on AUBoard15P

Aenerine

Hello,
I was trying to figure out the functionality of the "HDMI_TX_EN" pin with location constraint set to FPGA PIN Y23.
There is no information in the documentation on how this pin is routed and what exactly it controls. Based on its name I can only guess its functionality.
Would love to see a more detailed description on the board's HDMI topology, used silicon chips and initial configuration of those components.

For example, there is no information on what is the default configuration of the U56 (How is the OTP configured?) or what TMDS redriver chips are used.
The "List of Features" in the hardware guide list only "HDMI TX and RX Interfaces" (Without anything else), which I consider quite insufficient for the purposes of the documentation.
Please add the missing information.
Thank you

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  • 0

    There is a bare metal HDMI reference design posted in the reference document page on AUBoard-15P website.

    The enable pins map to the redriver chips. You can see the functionality in the reference design. The reference design is a modified version of the AMD reference design except support for the 8T49N241 is worked into the code.

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  • 0

    There is a bare metal HDMI reference design posted in the reference document page on AUBoard-15P website.

    The enable pins map to the redriver chips. You can see the functionality in the reference design. The reference design is a modified version of the AMD reference design except support for the 8T49N241 is worked into the code.

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  • 0 in reply to iksevas

    Hello and thanks for poing me to the reference design.
    I was however not asking for a reference design. I am asking to provide a clear documentation for the board that describes all relevant pinout and functionality.
    I had guessed that I need to tie the OE to VCC, which can be confirmed by looking at the reference design, however IT DOES NOT EXPLAIN WHY or what exactly is controlled by this pin. Besides, this was just an example of the missing pin.
    I still require a full access to the board schematic.
    Thank you

    By the way, try to read the schematic from the reference design or the HW 3 user guide. Thats really terrible.
    Who authorized to use poor-quality images in official PDF documentation? 
    image

  • 0 in reply to Aenerine

    The signal name doesn’t have an _n or _b on the end of it. That should tell you that it is an active high signal right?

    If you want to gain access to the schematic it looks like you need to work with an Avnet FAE to make the document request..