I have been trying to test pcie with asynchronus clocks. I have used the tutorial on programmable clock sources to update SFP+ clock to be 100MHz and used it as pcie ref clock. I have been having toruble establishing a link.
I wanted to know if the termiantion on the SFP+ clk line would cuase any issues. There could be other factors like incresed loss in the set up cuasing this error, but I just wanted to make sure this was a viable path.
