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Avnet Boards General Talking to the PHY with MDIO/MDC
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  • Replies 6 replies
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  • net1
  • Zedboard Hardware Design
  • ethernet shield
  • fmc carrier card
  • zedboardcmty
Related

Talking to the PHY with MDIO/MDC

andyy
andyy over 5 years ago

Hey, I have a problem with the Phys of the AES-FMC-NETW1-G module. The Phys are not responding to enquirys at the MDIO/MDC interface.

 

The boards are: AES-ZU-PCIECC-G - AES-ZU3EG-1-SOM-I-G - AES-FMC-NETW1-G.

 

Attached you can see that the Phy 1 is not responding:

image

 

Actually I do not know exactly how I can go one. Normally the Phy should speak to me at address 0x01. Some ideas/hints/help for me? Do I need to enable the MDIO/MDC interface at the board?

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  • michaelkellett
    michaelkellett over 5 years ago

    Are there several PHYs on one MDIO interface ?

    If there are they will have to be told their addresses which is often done by pin strapping.

    Are you actually addressing the correct PHY (you'll need to pick your way through the bits on the scope trace.)

    Has the board ever worked ?

    Where did you get the scope trace (ie is it at the pins of the module or PHY chip)

     

    MK

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  • andyy
    andyy over 5 years ago in reply to michaelkellett

    Hello Michael, thanks for the response. To your questions:

     

    Are there several PHYs on one MDIO interface?

    -> There are two phys at the FMC-NETW1 which are connected seperatly.

     

    If there are they will have to be told their addresses which is often done by pin strapping.

    -> From the datasheet of the phys I know that they can use the addresses from 0...7 only. So I did a loop throught all addresses. Same result... No data at MDIO.

     

    Are you actually addressing the correct PHY (you'll need to pick your way through the bits on the scope trace.)

    -> Yes I'll do. Don't know if I can record the signal with an logic analyzer. Maybe this would be the best case. At the board I come in trouble because the soldering pins are very small... Possible that I solder some additional lines for getting the signals with a clamp.

     

    Has the board ever worked ?

    -> I was using it with a realtime ethernet fieldbus ip core and yes the communication is up and running. But I had never used the management interface. I have here two completly separated board combination (FMC-NET / SOM / Ultrazed). Both have the same result. So I'm asking me if I have to activate the management interface. The ip core was working with some other phys from a different manufacturer too. But I guess if the problem is in the FPGA I do not get those signals at the phy.

     

    Where did you get the scope trace (ie is it at the pins of the module or PHY chip)

    -> I was measurering MDIO after the pullup resistor and the clock directy at the pin of the phy case. The triggering was setup to clock.

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  • michaelkellett
    michaelkellett over 5 years ago in reply to andyy

    I'm pretty much at the limit of general suggestions.

     

    I have had problems getting phys to come up due to reset not being cleared and pins being incorrectly strapped but you would expect a ready made board to be OK.

     

    I think you'll need to hope that one of the Avnet guys is looking.

     

    MK

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  • narrucmot
    narrucmot over 5 years ago

    Hi Andyy,

     

    You have mentioned you are using the Avnet UltraZed-EG SOM with PCIe Carrier and NETW1 FMC module, but you haven't mentioned what Vivado hw project and, presumably, what PetaLinux BSP you are using.

     

    Though each Ethernet PHY on the NETW1 FMC has its own MDIO interface, these MDIO interfaces also have to be enabled, along with the associated GEM interface, in the ZU+ Processing System (PS) in Vivado.  For example:

    2072.contentimage_192210.png

     

    By default in the BSP that Avnet posts online for the UltraZed-EG + PCIe Carrier only enables one GEM + MDIO interface.  If you need to enable more GEM + MDIO interfaces you will need to open included Vivado project in the BSP and update the PS configuration to match your needs.

     

    The schematics for the NETW1 FMC can be found here:

    http://www.ultrazed.org/product/network-fmc-module

     

    The PetaLinux BSPs for the UltraZed-EG can be found here:

    https://www.element14.com/community/community/designcenter/zedboardcommunity/ultrazed/ultrazed-eg#e14tab2

     

    --Tom

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  • andyy
    andyy over 5 years ago in reply to narrucmot

    Hello Tom,

     

    both of the Phys are connected directly to an industrial ethernet real time IP core. Actually there is no GEM involved even the one of the carrier card. There is no Linux. I have run a bare metal driver application at R5.0. The data exchange via real time channel is working. The both Phys are connecting and they transmit/receive data correctly. I need to talk to the management interface for getting the link state and speed...
    Thank you I have the schematics. I'll see the pullup resistor at MDIO line and I was using this for measuring with the probe. I also have the datasheets of the Phy. I can't see anything concerning an init routine.

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  • narrucmot
    narrucmot over 5 years ago in reply to andyy

    It sounds like you are using the Xilinx Time Sensitive Networking IP?  If so, you may have more success with answers to your questions on the Xilinx forums.

    https://forums.xilinx.com/t5/forums/searchpage/tab/message?advanced=false&allow_punctuation=false&q=tsn

     

    If you haven't already, you may want to register for access to the Xilinx TSV IP lounge.  This will give you access to documentation for the TSN IP.

    https://www.xilinx.com/products/intellectual-property/ef-di-25g-tsn-802-1-cm.html#documentation

     

    I suspect the issue you are seeing is that the MDIO interfaces on the PHYs are not connected to the TSN IP inside the Zynq UltraScale+ (ZU+) Programmable Logic (PL).  You will need the Vivado project to determine that.

     

    --Tom

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