Hi,
I am working on ZCU102 with FMC MULTICAM4 with the reference design provided here.
https://xterra2.avnet.com/xilinx/vitis_embedded_platform_source/zcu102/zcu102_mc4
I have few questions
1. why are we using/how do we calculate that line rate in MIPI Rx Subsystem as 1500Mbps?
I tried to calculate using this = (Total pixels in line)*(Total lines in frame)*(Frame rate)*(bits per pixel)*(number of cameras)/(Number of lanes) = 2200*1125*60*12*4/4 = 1782Mbps
2. Assuming that the video clock frequency for the capture pipeline in the above design is 300MHz is due to the requirements of video clock in PG232. As the maximum resolution supported by single camera is 1080p, can we do Clock domain crossing using FIFO's and use video clock of 148.5 MHz for the further video processing in capture pipeline?