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Avnet Boards General Video clock for FMC MULTICAM4 reference design
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  • zcu102
  • avnet multicam4
  • aes-fmc-multicam4-g
  • zedboardcmty
Related

Video clock for FMC MULTICAM4 reference design

alekhya
alekhya over 4 years ago

Hi,

 

I am working on ZCU102 with FMC MULTICAM4 with the reference design provided here.
https://xterra2.avnet.com/xilinx/vitis_embedded_platform_source/zcu102/zcu102_mc4

I have few questions

1. why are we using/how do we calculate that line rate in MIPI Rx Subsystem as 1500Mbps?

I tried to calculate using this = (Total pixels in line)*(Total lines in frame)*(Frame rate)*(bits per pixel)*(number of cameras)/(Number of lanes) = 2200*1125*60*12*4/4 = 1782Mbps

 

2. Assuming that the video clock frequency for the capture pipeline in the above design is 300MHz is due to the requirements of video clock in PG232. As the maximum resolution supported by single camera is 1080p, can we do Clock domain crossing using FIFO's and use video clock of 148.5 MHz for the further video processing in capture pipeline?

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  • albertabeef
    albertabeef over 4 years ago +2
    Alekhya, Excellent questions Note that when calculating bit rate, we normally do not calculate the blanking intervals, so the "average" bit rate for the video content would be: 1080P30 = (1920x1080 pixels…
  • albertabeef
    albertabeef over 4 years ago in reply to alekhya +1
    Alekhya, Correct, the designs currently support the following resolutions; 1920x1080 @ 30 frames/sec 1280x720 @ 60 frames/src Regards, Mario.
  • albertabeef
    albertabeef over 4 years ago

    Alekhya,

     

    Excellent questions

     

    Note that when calculating bit rate, we normally do not calculate the blanking intervals, so the "average" bit rate for the video content would be:

    • 1080P30 = (1920x1080 pixels)*(12bits/pixel)*(30 /sec) = 0.75 G bits/sec
    • 720P60 = (1280x720 pixels)*(12 bits/pixel)*(60 / sec) = 0.66 G bits/sec

    In order to determine the required bit rate on the GMSL and MIPI interfaces, we need to add the packet overhead for each of these protocols.

    • I don’t know the exact numbers, but we have sufficient room for this overhead

     

    Regarding your second question, yes, I agree.
    The 1080P30 and 720P60 streams are only running at 75MHz, so 148.5MHz should be more than OK.

    In reality, however, the output of the "MIPI CSI-2 RX" core contains the video content from the four streams, so 300MHz is required there.
    After the "AXI-Stream Switcher" core, the combined stream is broken down into four individual streams, which "could" be run at a lower rate.

     

    7558.contentimage_207738.png

    Regards,

    Mario.

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  • alekhya
    alekhya over 4 years ago in reply to albertabeef

    Thanks Mario for the clarification.

     

    For camera input in FMC-MULTICAM4,  Is maximum frame rate supported is 30 incase of 1080p resolution?
    (Earlier the calculations are based on 60fps for 1080p)

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  • albertabeef
    albertabeef over 4 years ago in reply to alekhya

    Alekhya,
    Correct, the designs currently support the following resolutions;

    • 1920x1080 @ 30 frames/sec
    • 1280x720 @ 60 frames/src

     

    Regards,

    Mario.

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