SDR Training

Hello,

I am trying to work on the SDR training using Simulink (the lab 2 hw). When I navigate to the to the downloaded files, I get a different file name than is provided in the pdf, "commtimrecresample_dsp_start" vs "commtimrecresample_dsp_v23_start." Also, when I try to simulate the QPSK Generator, I get the following errors:

External Model firv6_3_CModel:firv6_3_cmodel threw std::exception:
An error occurred during HDL compilation. ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 155: Syntax error near '"'

ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 156: Syntax error near '"'

ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 156: Syntax error near '"'

ERROR:HDLCompiler:806 - "fir_compiler_v6_3_control.vhd" Line 155: Syntax error near """.

ERROR:HDLCompiler:806 - "fir_compiler_v6_3_control.vhd" Line 156: Syntax error near """.

ERROR:HDLCompiler:854 - "fir_compiler_v6_3_control.vhd" Line 86: Unit <behavioral> ignored due to previous errors.

Error occurred during "Simulation Initialization".

Reported by:
'commtimrecresample_dsp_start/DFE for Radio Rx/Xilinx 2X Decimation Halfband Filter RX/FIR Compiler 6.3 phase_1'

Any help would be great.

Nathan

0 Former Member over 12 years ago

Xilinx Fir Compiler / System Generator 14.4 has issues with R2012b. Consequently, as noted in the documentation, ISE / SysGen 14.3 is used for the Simulink labs. Subsequently, for Xilinx Platform Studio (XPS), you will need 14.1. This is where the development was at when we finalized the SpeedWay labs.

To summarize the tools requirements:

MathWorks MATLAB & Simulink R2012b
DSP System Toolbox
Signal Processing Toolbox
Fixed-Point Toolbox
Simulink Fixed Point

Xilinx ISE Design Suite 14.3 System Edition (used for lab 2)
Xilinx ISE Design Suite 14.1 System Edition (used for lab 3)

DSP_1
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0 Former Member over 12 years ago in reply to Former Member

@SDR_1

Thanks for your reply. I installed 14.3 and everything is working for me now. I missed that the tutorial was designed using ISE 14.3. I had used 14.4 for the other Speedway training courses without much of an issue.

Nathan
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0 Former Member over 12 years ago

I've run into another issue trying to follow the labs in the SDR training. In Experiment 4 of Lab 2, I am unable to do the high level simulation with the symbol timing recovery integrated. I get the following error:

Making simulation target "commtimrecresample_dsp_baseband_sfun", ...

'commtimrecresample_dsp_baseband_sfun.bat' is not recognized as an internal or external command,
operable program or batch file.

Again, any help would be greatly appreciated.
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0 Former Member over 11 years ago

Good morning, I need help with the generation of the BIN file to the SD Card, I follow the steps of the laboratories. The simulation is perfect, the system generator compiles without problems, make the connection instance of the TX and RX module, I generate the BIN file Zedboard recognize the card over Linux or the board from Analog Devices Radio is live. Could someone give me a hint, follow the link attached my project. Thank you,
http://www.sendspace.com/file/k13lru
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0 Former Member over 10 years ago

Hi, where do you download the commtimrecresample_dsp_v23_start project file..? can you please give the link here.
Thanks in advance.
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