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FPGA fabric clock input?

Former Member

I can't seem to find an external clock to the FPGA fabric on the MicroZed. Does it have to get the clock from the processor subsystem or from one of the microheaders?

  • 0

    Hi,

    With respect to the information above, then would the following be valid:

    I have a 80 MSPS 16-bit TI ADC board (via FMC).

    I'm planning on getting the MicroZed Z7020 (where the PS is clocked at 667 MHz).

    Thus:

    using two-wire (LVDS) approach - (16bit x 80 MSPS)/2 = 640 MHz required bit clock rate for the ADC.

    Would my MicroZed be capable of handling the capture since its 667 MHz?

  • 0

    Hello Nocturnalpea,

    You should look into using the SERDES IP block(SelectIO Interface Wizard). This IP block is used for LVDS to bring the data into the fabric serial and convert it to a slower more manageable clock with the data in parallel. This inturn limits the HIGH speed to as few logic cells as possible which helps your timing. That is if you really do need the 640MHz, if you pass into the SERDES IP block you will only need a 40MHz clock to perform operations on the data.

    Another thing to note is depending on the pins used you may only hit 600Mb/s (LVDS) per lane.

    https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

    So as for your question of will it work. It depends. It turns into a question of will it work how you intend it to. Maybe, but if you use the SERDES IP block, then most likely yes.

    I am going to suggest that you ask any further questions in relationship to getting your TI FMC working over at the TI Forum as they will have more experience in implementing their own boards.

    https://e2e.ti.com/support/

    --Josh