what is the block 'ETH RESET DELAY & LVL XNSLTR' for? what will happen if we drop 'U21/Q6'?
output of U8 is 1.8V already.
Hi,
Refer to the Marvel datasheet for the reasoning for the delay.
-Josh
I found it in 4.8.1 T(PU_RESET) requirement is 10ms, which is very bigger than T(SU_XTAL_IN) (10clks). I think the delay circuit is for the T(SU_XTAL_IN), but the connected ASDMB is connected to 1.8V directly without any enable signal. the ASDMB will use 3ms after power good. in other words: 1. If we can ensure T(PU_RESET) match 10ms, we will reserve 7ms for T(SU_XTAL_IN) at least, which will match the 10clks requirement definitely. 2. If we can not ensure the 10ms of T(PU_RESET), there is no use for discussing the 10clks of T(SU_XTAL_IN). So I think the delay circuit for ethernet reset is not must in microzed, isn't it?
