the ethernet reset

niqingliang2003 over 7 years ago

what is the block 'ETH RESET DELAY & LVL XNSLTR' for?

what will happen if we drop 'U21/Q6'?

output of U8 is 1.8V already.

0 jafoste4 over 7 years ago

Hi,
Refer to the Marvel datasheet for the reasoning for the delay.
-Josh
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0 niqingliang2003 over 7 years ago in reply to jafoste4

I found it in 4.8.1
T(PU_RESET) requirement is 10ms, which is very bigger than T(SU_XTAL_IN) (10clks).

I think the delay circuit is for the T(SU_XTAL_IN), but the connected ASDMB is connected to 1.8V directly without any enable signal.

the ASDMB will use 3ms after power good.

in other words:

1. If we can ensure T(PU_RESET) match 10ms, we will reserve 7ms for T(SU_XTAL_IN) at least, which will match the 10clks requirement definitely.

2. If we can not ensure the 10ms of T(PU_RESET), there is no use for discussing the 10clks of T(SU_XTAL_IN).

So I think the delay circuit for ethernet reset is not must in microzed, isn't it?
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0 bhfletcher over 7 years ago

We had previous versions of MicroZed that did not implement the RC delay on RESET, and they worked fine. However, we added it to comply with the specification in the datasheet.
Bryan
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0 niqingliang2003 over 7 years ago in reply to bhfletcher

what is the delay circuit for? 10ms after power on ? or for 10 clks of ASDMB?
if for the 10ms, which symbol can implement it? I'm a newbie, could you explain the delay circuit for the 10ms delay?
if for the 10clks, I don't think it will work.
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0 jafoste4 over 7 years ago

Hi niqingliang2003,
May I ask why you are interested in this circuit? Are you working on your own customer board based off MicroZed?
-Josh
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0 niqingliang2003 over 7 years ago in reply to jafoste4

I'm a SW developer, and am studying hardware design, using microzed as a reference. So I will ask some question which may be taken for granted by hw.

I want to know _WHY_ for every detail.

maybe here is not the best place for that, do you have other advice? VERY THANKS!
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