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Mini-ITX self-test - PL DDR issue?

Former Member

Hello everyone,

Just wondering whether there's a self-test boot image available for the 7045 mini-ITX board. I'm seeing some odd behaviour (more below) which I'm 99% sure it just a configuration/software error but I'd like to be completely eliminate the hardware as a cause. I've found the Out-Of-Box design, but that's only a very basic test (essentially checks that the PS starts up).

 

The problem I'm having: I can only access 512MB of the PL DDR3 RAM. It's mapped into address range 0x8000_0000 to 0xBFFF_FFFF (ie 1GB address space) but everything from 0xA000_0000 to 0xBFFF_FFFF is the same as 0x8000_0000 to 0x9FFF_FFFF. If I write to 0x8000_0000, the same data appears at 0xA000_0000 and vice versa.

Software in use is Vivado 2016.1, Petalinux 2015.4, and a heavily-modified version of the Zynq 7045 Mini-ITX 2015.2.1 Petalinux reference design (I cut out almost all the original hardware blocks to put my own in, but I haven't touched the MIG).

 

Any ideas?

 

Thanks,

Evan

  • 0

    Evan,

      If you just want to validatate that all the memory is available in bare metal, the SDK can generate a memory test program.  By default, it only tests a portion of available memory (for a quick and speedy check that things are working), but you can easily modify the source to validate the entire available memory.

    Ron

  • 0 in reply to Former Member

    Ron,

     

    Thanks very much for the reply. I didn't know about that feature in the SDK; it'll definitely be useful. I've done a bit of software-level testing using peek/poke from Petalinux and that is definitely not able to access the upper 512MB of PL RAM.

     

    The problem I have is that I suspect there's actually a problem below the software level, either in the physical hardware (unlikely) or in the bitstream (more likely). What I was hoping to get was a "known-good" self-test bitstream which would distinguish between those scenarios; if a known-good bitstream that works on other mini-ITX boards works fine here then the hardware is fine and somehow Vivado is getting the bitstream generation messed-up; if it fails here then there must be a hardware issue with the board and we should look into replacing it.

    It looks like I can take the Petalinux reference design (which includes a pre-built bitstream) and use that with the SDK, so I'll give that a shot.

     

    Cheers,

    Evan

  • 0 in reply to Former Member

    Ron,

     

    I just gave that a shot, and the PL memory appears to fail. I've tested using the 2015.2 and 2014.2 Petalinux reference designs with the same results. A hardware problem with the board is now looking more likely. Thanks very much for your help.

     

    Cheers,

    Evan

  • 0 in reply to Former Member

    Hello,

    May be it's not really relevant you your subject, but my question is about MIG, PS and PL parts.

    I found some post that the only way to interface DDR is thought PS (since it has an integrated DDR controller) for Zedboard. Is this true for Mini-ITX as well? Is this correct for all Zynq devices? or only for Zedboard?

    What would actually happen if I create only a 'PL' project with MIG IP, since it's providing this option? Moreover it provides an option to have both PS with DDR3 access and a MIG generation as well with it's own DDR controller. Or am I missing something?

    Thank you in advance.

  • 0

    Hello Maxxx54,

    It depends on the Zynq board you are looking at. For instance if you look at the Mini-ITX hardware user guide http://zedboard.org/support/documentation/2056 page 14, it states that the Mini-ITX development board utilizes two 1Gb banks of DDR3 memory. One bank resides on the PS side of the Zynq-7000 AP Soc(like ZedBoard), and the other on the PL side. The PL bank pin out is generated by MIG.

    --Josh

  • 0 in reply to jafoste4

    Thank, Josh for reply!

    A few more aspects:
    1) Since on Zedboard DDR is only connected to PS side, this would be the only way to access it then (using integrated to PS controller). However it's still possible to insert say MIG controller to Zedboard'd vivado design, although I'm not sure how it'll then handle it further on in implementation parts.. 
    BTW,  since any DDR  controller would need a processing power (either ARM or say a Microblaze) would it be possible to connect MIG controller to ARM core? Or since in Zedboard MIG is not connected with DDR, there is not much use of such an experiments?


    2) Another question is more related to mini-ITX type boards, where 1G DDR is indeed split between PS and PL parts. In such a board I assume it would be possible to use both  MIG (with say Microblaze) and PS parts,  both would need to address different parts of DDR, but still be in the same design. Is it not? Then  it's also should be possible to use ARM to control MIG for DDR access? Question here is also regarding performance, if say I need to transfer data from ADC to DDR (in mini-ITX), which way would be more preferable using pure PS side or MIG + Microblaze or may be ARM and MIG?


    Thank you in advance.