I designed 7seg display driver in Verilog.
in xdc file, I define my clock as follows
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS33} [get_ports clk];
create_clock -add -name sysclk -period 20.000 -waveform {0.000 10.000} [get_ports clk];
L12 is WRCC Pin
and clk is my clock input pin in my RTL design
it does not seem clock is clocking..
Am I missing something?
Block design is not used.
In the Minized you cannot directly assign a clock pin location in user constraints file. No clock is connected to the Programmable Logic (PL)
The 33.33MHz clock is connected to the Processing System (PS) part of Zynq SoC and drives different PLLs from which all clocks for the SoC core and its peripherals are derived.
The Programmable Logic (PL) section of Zynq can source a total of 4 different clocks from this clocking hardware.
You can configure PL Fabric Clocks from Vivado ZYNQ7 PS IP
create your HDL code
`timescale 1ns / 1ps
module verilog_clocked_blinky(
input clk,
output led_g,
output led_r
);
// reg for counter
reg [25:0] count = 0;
assign led_g = count[23];
assign led_r = count[25];
always @ (posedge(clk)) count <= count + 1;
endmodule
route the clock signal
xdc file
set_property PACKAGE_PIN E13 [get_ports led_g_0] set_property IOSTANDARD LVCMOS33 [get_ports led_g_0] set_property PACKAGE_PIN E12 [get_ports led_r_0] set_property IOSTANDARD LVCMOS33 [get_ports led_r_0]
This is the easy way
