QUESTION 1:
Let's say I configure PCIe in Zynq 7000 FPGA as a root complex, where does the PCIe clock come from in this case?
I look at the schematics and it appears that the PCIe_REFCLK is an output of the edge connector?
Does that mean the PCIe_REFCLK is an input reference clock the GT Transceveiver inside of the FPGA?
Where does the PCIe_REFCLK get generated? In order words, do I need to do anything special to get a clock in case of using root complex PCIe configuration instead of PCIe end-point configuration...
Basically, I need to use the Picozed to connect to an end-point PCIe device, with picozed acting as the Host Root Complex...
QUESTION 2:
Is PCIe_RST_N generated by the FPGA in the case of the root complex mode? or is it alway an input regardless of root complex or end-point mode. When I look at schematic it show it as an output to the edge connector which would seem to indicate that I always generate PCIE_RST_N. is this correct?
My conclusion is that I need a “PCI Express Gen1/2/3 Test & SMA Breakout Board” to generate an external differential clock to the pcie edge connector as an input to the fpga.
