Actions
Forum Thread Details
  • Replies 5 replies
  • Subscribers 322 subscribers
  • Views 4777 views
  • Users 0 members are here
Related

How to generate PCIe clock when configured as PCIe root complex...

wm2015email

QUESTION 1:

 

Let's say I configure PCIe in Zynq 7000 FPGA as a root complex, where does the PCIe clock come from in this case?

 

I look at the schematics and it appears that the PCIe_REFCLK is an output of the edge connector?

 

Does that mean the PCIe_REFCLK is an input reference clock the GT Transceveiver inside of the FPGA?

 

Where does the PCIe_REFCLK get generated?   In order words, do I need to do anything special to get a clock in case of using root complex PCIe configuration instead of PCIe end-point configuration...

 

Basically, I need to use the Picozed to connect to an end-point PCIe device, with picozed acting as the Host Root Complex...

 

QUESTION 2:

 

Is PCIe_RST_N generated by the FPGA in the case of the root complex mode?  or is it alway an input regardless of root complex or end-point mode. When I look at schematic it show it as an output to the edge connector which would seem to indicate that I always generate PCIE_RST_N.  is this correct?

 



image

 

My conclusion is that I need a “PCI Express Gen1/2/3 Test & SMA Breakout Board” to generate an external differential clock to the pcie edge connector as an input to the fpga.

Parents

  • Hi there,

     

    • The PCIe root clock comes from wherever you need it to.  Generally, a high quality PCIe compatible clock.  In the case of the PicoZed the board is setup for EDGE, not ROOT.  that you mentioned, you can use the IDT programmable clock.  If you use the reference design that I posted in your other query, you will see that the clock output is already setup for 250MHz, but it is setup as an edge device.
    • PCIe_REFCLK comes in on the card edge.  Trace the signal in the schematic and you will see that it is an input to the IDT (now Renesas) clock, the clock comes IN on the card edge, like any other endpoint device
    • Yes, it is an input to the FemtoClock, and then passes to the MGT after it is cleaned up
    • the REFCLK is generated by the source root complex - in this case it should be a PC motherboard

     

    If you need this to be a root device, the FMCv2 was not designed for that, you will have to ensure all signaling is present and I suspect likely you will have challenged and will need to reconfigure the XDC and other bit to flip everything around.  You will need to have an external clock though, as the FemtoClock has been setup as an input to the MGT and you will need to supply a common clock to all PCIe device on the same bus.

     

    • The PCIe_RST_N would need to be generated by the root complex in the case of the 7030 being the root device.

     

    That board you selected can break things out and generate your clock.  I have used that as loopback testing and can say it works well.  You will need a way to convert the data and clocks back to your edge device you plan to connect to, but SI problems aside, it will allow you to break out this device.

     

    In the case of the PicoZed FMCv2, the board cannot source the clock.  It is not wired like that.  The V1 could do that, but this one cannot.  It was setup as an endpoint device.  Regardless, the Zynq device should not be sourcing the clock.  It cannot output a high enough quality clock.  That is why you would use a device like the FemToClock or the adapter board you linked to, which would be able to source such a clock.

     

    Long story short, if you use that breakout card, you can use IT to insert the clock into the PicoZed, setup the PicoZed as a root, then you need to send that adapter board's clock over to the endpoint device, along with the data lines.

    I am not sure this is the best way to do this.  There can be a lot of SI issues.  It might be better to spin a new carrier card for the PicoZed or you can look at something like our Mini-ITX board, which already has all of that setup properly.

     

    Mini-ITX

     

    --Dan

  • in reply to drozwood90

    maybe a better choice... can configure one card a endpoint and other card as root complex device and connect this with this card that had PCIe clockdevice

    image

  • in reply to wm2015email

    Hi there,

     

    From the screen shot, I do not see how this will connect beyond the single card input.  Maybe I am missing something from the picture?

    You need a board that has a root connector.  You will need to be concerned about the SI as well.  So watch for that.  The PCIe protocol is pretty robust, but you want to be sensitive to the SI so you do not burden it and lose performance.

    With the hightechglobal solution, you could just get two boards (which is what I thought you were doing).  One runs as the root and the other as the endpoint.  Then you wire them together using properly rated COAX.  Using only 1 board as a clock source (the one setup as root).

     

    --Dan

Reply
  • in reply to wm2015email

    Hi there,

     

    From the screen shot, I do not see how this will connect beyond the single card input.  Maybe I am missing something from the picture?

    You need a board that has a root connector.  You will need to be concerned about the SI as well.  So watch for that.  The PCIe protocol is pretty robust, but you want to be sensitive to the SI so you do not burden it and lose performance.

    With the hightechglobal solution, you could just get two boards (which is what I thought you were doing).  One runs as the root and the other as the endpoint.  Then you wire them together using properly rated COAX.  Using only 1 board as a clock source (the one setup as root).

     

    --Dan

Children
No Data