Actions
Forum Thread Details
  • State Not Answered
  • Replies 4 replies
  • Subscribers 177 subscribers
  • Views 375 views
  • Users 0 members are here
Related

LwIP Example UART problem

Former Member

Hi,

I'm new to the ZedBoard and currently I'm trying to run the LwIP examples,
provided by Xilinx, on the Board.
(XAPP1026)

I have connected the USB-JTAG and USB-UART to my host machine.
A Serial Terminal has been configured as always for the ZedBoard.

An Ethernet cable is connecting the ZedBoard and the host machine. The host machine IP configuration is identical to the recommended values in the example.

The Boot Mode Jumper are: PLL Used, JTAG Boot, Cascaded JTAG: MIO[6:2] = 00000.

I've set up the SDK-Project according to the manual, and ran the Software as explained. Hoever, no Serial Terminal output is provided.

There are two things that are not mentioned in the manual, and thus could be the
source of the Problem:
The "fsbl" Project displays an error:

make: *** No rule for Target u00BBC:/PROJECT_FOR_RELEASE/zc702_GigE/HW/project_1/project_1.sdk/design_1_wrapper_hw_platform_0/ps7_init.cu00AB,

The SKD-log displays a warn:

13:57:03 WARNt:  [Hsi 55-1559] Software Design already exists with Name C:PROJECT_FOR_RELEASEzc702_GigEHWproject_1project_1.sdkraw_apps_bspsystem.mss

Has anyone experienced something similar?





  • 0

    XAPP1026 targets the Xilinx ZC702 eval board not the ZedBoard. In order to run the LwIP examples you will need to modify the hardware design to target the Zedboard and rebuild the project. You will also need to modify the locations of the image.mfs file. There is a version of the of XAPP1026 (using ISE 14.5) that has been adapted to the Zedboard and is available for download here:

     

    http://zedboard.org/support/design/1521/11

     

    There is a forum thread addressing this issue that might be interesting. Note that the link to the ZedBoard xapp10126 project above is correct while the one in the forum post is outdated:

     

    http://zedboard.org/content/porting-xapp-1026-zed-board

     

    -Gary

  • 0

    Thanks for Link,
    but I am still stuck. I created a new SDK workspace, where I
    added the Repository and imported the Project. But they all fail with
    an error, and I cannot generate the BSP-Resources, because the
    system.mss file can not be found.

    15:57:02 ERRORt: Failed to generate BSP due to invalid mss path

    also

    15:57:02 WARNt:  [Hsi 55-1484] MSS file doesn't have NAME. So assuming NAME as system
    15:57:02 ERRORt:  [Hsi 55-1594] Core gpio of version 3.00.a not found in repositories

    I assume, that there is Problem with the PL-build somehow.
    I have Vivado 2014.3 running on my System, is there
    ans possibility that I can rebuild and export he PL?

  • 0 in reply to Former Member

    I also tried to generate an own bsp to run the raw_apps.
    But I got a warning that some tcl. scripts mismatch the
    hardware, and that I should write my own tcl or rebuild
    with Vivado 2014.3

  • 0

    The link is to a version of XAPP1026 adapted for the ZedBoard that is based on ISE 14.5. If you want to use this project unchanged you will probably need to run it  using the Xilinx ISE tool suite.

     

    If you want to use Vivado then you will need to start with the Xilinx XAPP1026 project and make changes in the project, similar to what was done in the adapted project from the link and the linked forum post, to target the Zedboard and rebuild the project. Also note that the ZedBoard does not have as much DDR memory as the ZC702 board so you may need to change the location of the image.mfs file.

     

    -Gary