I'm new to the ZedBoard and currently I'm trying to run the LwIP examples,
provided by Xilinx, on the Board.
I have connected the USB-JTAG and USB-UART to my host machine.
A Serial Terminal has been configured as always for the ZedBoard.
An Ethernet cable is connecting the ZedBoard and the host machine. The host machine IP configuration is identical to the recommended values in the example.
The Boot Mode Jumper are: PLL Used, JTAG Boot, Cascaded JTAG: MIO[6:2] = 00000.
I've set up the SDK-Project according to the manual, and ran the Software as explained. Hoever, no Serial Terminal output is provided.
There are two things that are not mentioned in the manual, and thus could be the
source of the Problem:
The "fsbl" Project displays an error:
make: *** No rule for Target u00BBC:/PROJECT_FOR_RELEASE/zc702_GigE/HW/project_1/project_1.sdk/design_1_wrapper_hw_platform_0/ps7_init.cu00AB,
The SKD-log displays a warn:
13:57:03 WARNt: [Hsi 55-1559] Software Design already exists with Name C:PROJECT_FOR_RELEASEzc702_GigEHWproject_1project_1.sdkraw_apps_bspsystem.mss
Has anyone experienced something similar?