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Software Application Development Zedboard printing garbage/junk over UART
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Zedboard printing garbage/junk over UART

crank1
crank1 over 2 years ago

Hello, I have been working through some basic examples on the Zedboard, i.e. creating a simple PL fabric to switch an LED upon a button press. The board will program fine, and the system will work (i.e. LEDs and buttons work fine), however, whenever it prints something to the terminal, it appears as junk. I have a cable plugged into the J17 (prog) port and the J14 (UART) port. I have tried every baud rate possible, I understand that the standard is 115200, however no baud rate works (have tried on Vitis Terminal, PuTTy and TeraTerm). I have installed the Cypress (now distributed by Infinion) USB to UART drivers and the board comes up on the device manager as a serial device. I have also tried plugging the J14 port into my Macbook and using screen, but it still has the same issue. All the boot jumpers (JP7-JP11) are grounded. I am using Windows 10 and Vivado and Vitis 2022.2. Are there any other reasons as to why it would be printing junk? I have played around with the Linux install on the SD and all works fine when using a serial terminal, so I don't think it is a driver problem. Thanks.

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  • michaelkellett
    michaelkellett over 2 years ago +2
    Connect a scope to the serial port. Ideally one which can decode UART protocols. This will enable you to actually measure the baud rate and comprehend the data. Could be parity/baud rate/ handshake/number…
  • Gough Lui
    Gough Lui over 2 years ago +2
    Perhaps the system is expecting a clock crystal source of a certain frequency and the actual crystal you are using is a different frequency, resulting in everything being "at the wrong speed". Check…
  • saadtiwana_int
    saadtiwana_int over 2 years ago +1
    I think what Gough Lui mentioned could very well be the issue, because you are getting serial output, just not at the right baud rate probably. And since with the Linux image it's working fine, so it can…
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  • kkimmich
    0 kkimmich over 2 years ago

    Another thing I found today is there are two repositories of BDF files with zedboards. The avnet one is: https://github.com/Avnet/bdf

    Those files are different than the digilent one, which is what I've been using so far.

    There are different revisions of the board. I have a Rev C board (printed on the board under the serial number). There are also rev D and E versions. I am not sure what changes between the boards. There's no discussion of these differences and the BDF repos in the zedboard online documentation.

    Anyway, the clock input frequency in Vivado configured with the Avnet BDF is 33 MHz, not 50 MHz. I did try running it in the helloworld/Vitis environment but it just didn't display anything on the console.

    I'm trying the petalinux build based on that Avnet BDF vivado project now.

    The board I have is "old".

    Hey that worked!

    helloworld in vitis did not work, but petalinux did. I used this to create the project:

    petalinux-create --type project -s avnet-digilent-zedboard-v2020.2-final.bsp --name avnetlinux

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  • kkimmich
    0 kkimmich over 2 years ago

    Another thing I found today is there are two repositories of BDF files with zedboards. The avnet one is: https://github.com/Avnet/bdf

    Those files are different than the digilent one, which is what I've been using so far.

    There are different revisions of the board. I have a Rev C board (printed on the board under the serial number). There are also rev D and E versions. I am not sure what changes between the boards. There's no discussion of these differences and the BDF repos in the zedboard online documentation.

    Anyway, the clock input frequency in Vivado configured with the Avnet BDF is 33 MHz, not 50 MHz. I did try running it in the helloworld/Vitis environment but it just didn't display anything on the console.

    I'm trying the petalinux build based on that Avnet BDF vivado project now.

    The board I have is "old".

    Hey that worked!

    helloworld in vitis did not work, but petalinux did. I used this to create the project:

    petalinux-create --type project -s avnet-digilent-zedboard-v2020.2-final.bsp --name avnetlinux

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  • crank1
    0 crank1 over 2 years ago in reply to kkimmich

    Thats great to hear, I haven't used the petalinux tools yet to create a linux boot image, but I will attempt that over the weekend - thanks so much for your help!

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  • rfdspguru
    0 rfdspguru over 2 years ago in reply to crank1

    Not sure if you're still "cranking" on this... rather than the Petalinux build, if you go into "Open Block Design" in Vivado, double click the Zynq block, then choose Clocking Configuration on the left, you'll see the input frequency if 50 MHz.  I set this to 33.33333, Generated a new bitstream, re-exported hardware, and ran the helloworld in SDK... it works.

    I'm using Vivado 2019.1.3 (hence no Vitis) and a Digilent rev D board.  

    Note the rev D schematic shows a 33 MHz "PS" clock (IC18) and I verified that with a scope.

    image

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