Is it possible to implement an i2c master block in Ultra96 that can provide SCK up to 1MHz?
Is it possible to implement an i2c master block in Ultra96 that can provide SCK up to 1MHz?
Both the PS I2C and PL I2C (axi_iic) peripherals for the Zynq UltraScale+ are only configurable for either 100 or 400 KHz per the I2C specification. However, there may be other 3rd party I2C IP cores available that can be implemented in the ZU+ PL and configured for a 1 MHz I2C SCL.
Both the PS I2C and PL I2C (axi_iic) peripherals for the Zynq UltraScale+ are only configurable for either 100 or 400 KHz per the I2C specification. However, there may be other 3rd party I2C IP cores available that can be implemented in the ZU+ PL and configured for a 1 MHz I2C SCL.