Hi,
According to Xilinx TRM document, UART0 uses MIO_34 (TX) and MIO_35 (RX), and UART1 uses MIO_32 (RX) and MIO_33 (TX).
On the Avenet Carrier Card, UART0's TX MIO_34 is connected to U16 CP2105's TXD_SCI and RX MIO_33 to U16's RXD_SCI. UART1's TX/RX pins are also swapped.
How to understand this design?
Thanks.
-WWQ
Hi there,
I'm not sure I follow. The pins are configured in the PS by the board preset.
What is swapped about them?
--Dan
Hi, Dan,
You are right about these pins from Xilinx PS configuration. They are consistent with Xilinx TRM.
The confusing comes from the notes in Avnet CC schematic and UG:
Where is swizzled or swapped coming from?
Thanks.
-WWQ
