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UltraZed-EV GC LVDS Clock DC Coupling

revky

Hi,

I am using a SI5341 to generate a 400MHz to use as global clock on the UltraZed-EV+.

The SI5341 output buffer supply is +3V3 and the FPGA HP bank is +1V8.

The output buffer common mode voltage for this is 1.1V to 1.3V and swing is 350mV to 510mV. Due to the fact that the FPGA is on the SoM I cannot use ac coupling next to the FPGA.

My question is can I get away with DC coupling if the LVDS voltages are within range of the FPGA or should I use AC-coupling before the SoM Module?

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  • You may be able to get away with the DC coupled lines if the voltages fall in range of the FPGA I/O. Ultimately you could be playing games with the voltage standard you are using in your Vivado design to make it work if it differs from the LVDS requirements of the FPGA I/O. It would be prudent if you added termination to your design that converts to the proper voltage range. Many times, it's not an ideal solution, but you could add the termination / AC coupling as close as possible to the JX connector of your Carrier Card. Give yourself options to avoid spinning the board later.

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  • You may be able to get away with the DC coupled lines if the voltages fall in range of the FPGA I/O. Ultimately you could be playing games with the voltage standard you are using in your Vivado design to make it work if it differs from the LVDS requirements of the FPGA I/O. It would be prudent if you added termination to your design that converts to the proper voltage range. Many times, it's not an ideal solution, but you could add the termination / AC coupling as close as possible to the JX connector of your Carrier Card. Give yourself options to avoid spinning the board later.

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