Another Usefull Reference Projects

oen_br,

I'm glad you found my tutorial useful.  I'm sorry your having trouble putting everything together. There are a million how-to's I would like to write for Zynq, and I am getting to many of them - but there are only 24 hours in the day!

First, I would highly recommend moving to PlanAhead - you are going to have a hard time with things if you stick with ISE. From a top-level view, you will want to create extra signals on your port statements within your pcore (custom peripheral) that you instantiate within XPS. Then you will attach these signals as external ports within the Ports tab. After that, when you bring the MHS file back into PlanAhead and create the HDL top module, you will see that your ports are available to attach to the outside world. Add a constraint file with the net assignments, and then export to SDk. Hopefully that will get you going in the right direction.

I will work on a deep dive for writing pcores.  Stay tuned!

Hello zynqgeek,

Thankyou for your help.

I modified two files, directory .srcs/sources_1/.../pcores/led_reg_v1_00_a/hdl/
verilog/user_logig.v (I'm using verilog)
vhdl/led_reg.vhd
to include the ports LD0, LD1,...,LD7 (LEDs), but it didn't work. The LED ports are not connected to the IOBs and the EDK Ports tab didn't show them either.
I have also modified the wrapper file that instantiates the led_reg, but it looks like this wrapper file is automatically generated, so my modifications are lost everytime I run the PlanAhead synthesis tool.
So, I'm still out of luck.

I'll read the PlanAhead manuals. Maybe I can find the "Path to Enlightenment".

Hello,

When I tried to use LEDs with my custom peripheral, I had troubles with constraints: the ports I added were not recognized.
Here is what I do to make it work:
- I change user_logic.vhd and top level zed_leds.vhd => my new ports are "LEDS : out std_logic_vector(7 downto 0);"
- in XPS, I add my custom peripheral named zed_leds
- in XPS, in "ports" tab, at zed_leds line, my ports are not visible...
- close XPS and change zed_leds_v2_1_0.mpd (zed_leds_pl.srcssources_1edkproc_modulepcoreszed_leds_v1_00_adata) => add "PORT LEDS = "", DIR = O, VEC = [7:0]" in "PORTS" section
- save and relaunch XPS => in "ports" tab, LEDS is now visible!
- connect to "External Ports::zed_leds0_LEDS_pin"
- exit XPS
- create .ucf file => "NET zed_leds_0_LEDS_pin[0] IOSTANDARD=LVCMOS25 | LOC=T22;" for led0, and so on.
- enjoy

I am not sure this is the right way but, well, if it can help...

oen_br,

if you create custom pcore, modify the HDL files, import it back to XPS, add it to the design than the ports will appear and you can make it external.

I recommend this tutorial (and the consequent parts):
http://www.youtube.com/watch?v=MC1amstP_8A

Ufa! It worked!
I used the import back method.
To save someone else time, these are some, maybe not so obvious, hicups I had:
a) When you are importing the peripheral, at some point it asks you to set the AXI4_lite parameter, deselect IO_space, select memory_space and set C_baseaddr and C_highaddr.
b) At the XPS Ports tab, when you make your ports external, rename them to match the UCF file (the names you want for your pins).
c) When I tried to Run Synthesis, there where an error about the wrapper file, it had not the ports declared. This file is created when you "Create Top HDL" in the PlanAhead. In my case, I had done it before changing my peripheral.
I don't know yet how to regenerate this file, and as I accidentally deleted it and didn't know what to do, I started a new project, generated the right bitstream before "Create Top HDL", and then it worked.

Thanks for the help.

Thank you for posting this topic....
  I have vhdl code and i want to give inputs to this vhdl code from the C code to the fpga input pins and reading the values of fpga output pins....
I verified this code by dumping directly from Cable by giving the input values from file in vhdl,Now i want to give this input values from C code,Is it possible to mention the ports in vhld code and communicate with the AXI interface,Please help me how to declare input and output ports in top hdl and giving the input values from the C code....
Thanks in advance...

Thank you oen_br for giving that information.....
I did same steps as u followed but in ucf file i declared LED pins as...
NET "zed_leds_0_LEDS_pin[0]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[0]" LOC = T22;

NET "zed_leds_0_LEDS_pin[1]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[1]" LOC = T21;

NET "zed_leds_0_LEDS_pin[2]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[2]" LOC = U22;

NET "zed_leds_0_LEDS_pin[3]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[3]" LOC = U21;

NET "zed_leds_0_LEDS_pin[4]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[4]" LOC = V22;

NET "zed_leds_0_LEDS_pin[5]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[5]" LOC = W22;

NET "zed_leds_0_LEDS_pin[6]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[6]" LOC = U19;

NET "zed_leds_0_LEDS_pin[7]" IOSTANDARD = LVCMOS25;
INST zed_leds_0_LEDS_pin[7]" LOC = U14;

But at the genreration of .bit file in plan-ahead it is giving error as.....

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
   not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
   This may cause I/O contention or incompatibility with the board power or
   connectivity affecting performance, signal integrity or in extreme cases
   cause damage to the device or the components to which it is connected.  To
   prevent this error, it is highly suggested to specify all pin locations and
   I/O standards to avoid potential contention or conflicts and allow proper
   bitstream creation.  To demote this error to a warning and allow bitstream
   creation with unspecified I/O location or standards, you may apply the
   following bitgen switch: -g UnconstrainedPins:Allow
ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.
Help me how to resolve this error and give me how to write C code to assign values to these leds to glow..........

Thanks in advance.....