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ZedBoard DDR3 interface address space?

Former Member

Hi,
According to ZedBoard user guide, The multi-protocol DDR memory controller is configured for 32-bit wide accesses to a 512 MB address space.

But I was wondering, how would I be able to target only ONE of the Micron MT41K128M16HA-15E components?

In other words, for my specific application, I have two VDMAs that are streaming to DDR. But I would prefer to know that the data from one VDMA is streamed into only one of the Micron memory components, and my data from the second VDMA targets ONLY the second memory component!!

Thanks in advance,
--Rudy


  • 0

    I don't think it is possible to do what you want. There is only one memory controller inside the Zynq, and it shares the address control signals between the two chips.

     

    It is possible to do byte writes. You could try writing exclusively bytes 0 and 1 for one set of data and bytes 2 and 3 for the other set. That would segregate the data between the two chips, but that seems really confusing to me.

     

    Bryan

  • 0

    Bryan,
    Thanks for the reply. But, is this how usually what happens when you write a 32-bit wide data into a two sets of 16-bit wide memory?

    Is that right that the first 16-bit gets stored in one RAM, and the other 16-bit gets stored in the second RAM?

    Because if this is the case, I can do this for my application, since in this specific application I don't really care about what I am writing into the DDRs !!

    But how do I know this is how the data is getting managed in the DDRs?
    Why not Byte-0 and Byte-1 getting stored in one DDR, and Byte-2 & Byte-3 is also in the subsequent address of the same DDR ?!
    I am sorry that if this is an obvious question, but I just didn't know how the 32-bit data is stored in two 16-bit SDRAM !
    Is this true for all sorts of board, which uses SDRAMs in parallel, or is this only true for the ZedBoard case?

    Thanks,
    --Rudy

  • 0 in reply to Former Member

    Rudy,

    Yes, that is definitely the case here. The ZedBoard was designed to have a 32-bit wide interface between the memory and the Zynq. The schematic and layout connect the configuration with bits 0 through 15 going to one chip and 16 through 31 going to another. This is the fastest, most efficient way. For every 32-bit word that you read or write, 1/2 is associated with one chip and 1/2 with the other.

     

    I believe this would be the case for every 32-bit processor that you see with 2 x16 chips attached to it.

     

    Bryan

  • 0

    Will there be a way for me to verify that I performed this correctly?

    Because I am afraid if try to read back from memory with the processor (in software), I will always get a 32-bit wide data back, since the processor only communicate with SDRAM on 32-bit wide boundary, correct?

    So, could you recommend any method for verification?
    Will there be anyway to temporarily disable one of the DDRs, and when I am reading back a 32-bit wide data, I would only see that 16-bit of this data is valid, which would correspond to either (Byte-0 & Byte-1), or (Byte-2, and Byte-3) !
    Or, maybe there is an easier way to verify this, but I just cannot see it?

    Thanks,
    --Rudy