Zedboard Tutorial issues on vivado 2015.1

Hello all, I'm starting to work with the ZedBoard and as i'm going through the tutorial provided with the website. I manage to fix the first errors that I faced but right now I'm stuck in exercise 4. I've followed all the steps carefully but i can't generate my bitstream. I got the following error messages:
[Common 17-55] 'set_property' expects at least one object.It
seems to me that something went wrong on my block design (you can check it here - http://postimg.org/image/5trz6zqad/). Should I get a 16 bit vector in the IRQ_F2P entrance of my ZNYQ7 PS block? Also I can't spi_0_ss_iobuf component instaciation. any chances all this could be related? I'm running vivado 2015.1 in a windows 8.1 64bits OS

0 Former Member over 10 years ago

Could you be more specific as to which tutorial you are using as there are quite a few on the website. Also what version of the Vivado tools was the tutorial you are using targeted for?

That said, a 'set-property' error could be an issue with your .xdc constraints file not matching up correctly with your design.

-Gary
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago in reply to Former Member

Hi Gary, thank you for your reply
I'm trying to follow the tutorial available at
zedboard.org/content/zynq-zedboard-vivado-workshop
the tutorial was target for Vivado 2014.1
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago

There can be minor differences as you move between different versions of the Vivado tools. I would suggest working through the tutorial in the version it was targeted for, Vivado 2014.1 in this case, first.

As mentioned above, the error you are getting seems to indicate a difference between your design and the constraints file. It is likely that either the newer version of the tools used a different naming convention or you may have made a typo error while entering your design. I notice that the output port for the axi_quad_spi IP is named 'spi_rtl' in your block diagram but the 'set_property' constraints in the tutorial are different. I would look there if you do want to attempt to use Vivado 2015.1.

-Gary
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago

Found the problem by comparing the elements in my wrapper file(pastebin. com / m9kX3E4n) and made some changes at the constrains that I was entering(final version: pastebin. com / ZHRvpmZJ), manage to run the implementation without any critical errors.

Thanks for the replys Gary

-Joao
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago

Hello Joa0!

It seems I am doing much the same thing as you! Although I have a Rev D Zedboard.

Anyway I can't seem to get the LD9 to light in Exercise 2. Can you describe how you fixed this error?

Sorry have also posted a question about this elsewhere before I noticed this post...
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago in reply to Former Member

hey chesser, if you still struggling with it
have a look at this
http://zedboard.org/content/zedboard-revision-d-bug-issues-emio-related
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago

The issue comes up because Vivado somehow does not want to let the user type out the constraints in the XDC file.

If you "Open Elaborated Design" in "RTL Analysis" in the flow navigator (after synthesizing your design without pin assignments), it allows you to open the IO planning layout. In this layout , you can do your pin assignments and save them. Vivado will then not give you the set_property error.
Note, you can select the IP planning layout from the drop down layout menu on the bar below the menu bar . It will show up when you open the elaborated design.
Hope this helps!
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 10 years ago in reply to Former Member

Sorry for the typo in my above post, its IO planning and not IP planning
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel