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ZedBoard Hardware Design Understanding Address Map
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Related

Understanding Address Map

jmales
jmales over 10 years ago

Please refer to page 113 of http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and approximately 1 Gbyte of memory available to write into the DDR, correct? I thought the Zedboard had only 512 Mbytes of DDR memory...

Also, in that table, it says that I have approximately 2Gbytes (4000_0000 to BFFF_FFFF) of address available for PL. What does this space mean exactly? What can I save in here?

Thank you

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  • Former Member
    0 Former Member over 10 years ago

    The Zynq TRM address map tables on page 113 indicate the addressable ranges available to the ARM CPUs and other Bus Masters within the Zynq device. These are the maximum address ranges assigned. They do not imply that a specific hardware implementation, such as the ZedBoard, actually completely fill these ranges. So, as you have noted, the ZedBoard only has 512 MBytes of DDR memory implemented on the board.

     

    The PL address range can be used by AXI peripherals and IP implemented in the Programmable Logic of the Zynq device. You might want to take a look at the Avnet Zynq HW and SW Speedway workshop material for a description of the Zynq memory areas and how to implement designs in the Zynq device.

     

    Developing ZynqRegistered-7000 All Programmable SoC Software (Vivado 2013.3 and 2014.4.1)

    Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3 and 2014.4.1)

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    sorry, i still not understand this question completely. i am confused about the 512M DDR Memory and 4G Address Map, what is the relation ship about the two concept.

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  • Former Member
    0 Former Member over 9 years ago

    Hello,

    4G is the maximum addressable area given that there are 32 address bits. The table referred to by jmales above maps how that 4G of address space is allocated for use in the Zynq device.

    512M is the actual amount of DDR memory that is physically installed on the ZedBoard. Other Zynq based boards may have more, or less, DDR memory.

    -Gary

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    thx for your reply. i think i have understood this question by you help.

    BTW, i want to enable the two ethernet function  on my customize board. i can use it independently, but can not work up when both are enable. Do you have any advise or any material about this?

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    You will need to provide more detail about what you are trying to accomplish.

    Is your custom board an add-on board (FMC) to the ZedBoard or a completely custom Zynq based board. If so what Zynq device?

    Are you attempting to use the two Ethernet controllers in the Zynq PS (Processor System), PL (Programmable Logic) based Ethernet MACs, or a combination of both?

    Do the PHYs for your two Ethernet controllers share a common MDIO control path or are they separate?

    Are you attempting to get the ethernet channels to work in a 'bare metal' mode or using Linux or some other OS?

    These links may also be helpful as working examples of multiple ethernet ports on a ZedBoard:

    http://www.fpgadeveloper.com/category/tutorials

    http://ethernetfmc.com/

    -Gary

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  • Former Member
    0 Former Member over 9 years ago

    thx for your reply and sorry for my less information about the two ethernet question.

    we design a custom board with ZC7020. And we need to use two ethernet port. the two port are all connected to PS Side with RGMII, and they all use the same MDC and MDIO signal from MIO50 and MIO53.

    BTW, the two PHYs are the same (Marvell 88E1512).  PHY0 addrss is 0, and PHY1 address is 1 by CONFIG pin to set it.

    i configure the vivado environment and then export to SDK, and then add a new Application (Peripheral Test application) to test the peripheral device. what makes me confuse is that: it can detect PHY address separately . However, when i enable the two ethernet function in Vivado and repeat to do it at SDK (ofcourse, the code at SDK is to check two ethernet devices). it cannoy detect phy1 address but can detect phy0 address.

    Is there anythig i miss to edit when i want to use two ethernet? thx very much for any reply.

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