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ZedBoard Hardware Design connection between CPU and PL
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connection between CPU and PL

Former Member
Former Member over 11 years ago

hi all!

My question is how can i send and recieve data through the CPU that in the board to the FPGA,when i use the Tera Term (for example) and i write the data on my PC. because i can program only the FPGA by IMPACT but i can't send data to the FPGA.

I have enother question when i write C code and running it on the CPU that in the board how can i send data to the pmod? I mean is there eny comand that can do that?

thanks

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  • Former Member
    Former Member over 11 years ago +1
    In general the Zynq system talk between CPU and FPGA through Axi-bus. If you read the Axi documentation there are three types: Axi, Axi-lite and Axi-stream; each have different data rate and complexity…
  • Former Member
    Former Member over 11 years ago +1
    For sending one bit of data to pmod, there are a couple way of doing it. One is enable PS's EMIO and use constraint to connect the pin to a PMOD port. Check out Zedboard CTT (for Vivado 2013.2) chapter…
  • Former Member
    0 Former Member over 11 years ago

    In general the Zynq system talk between CPU and FPGA through Axi-bus.  If you read the Axi documentation there are three types: Axi, Axi-lite and Axi-stream; each have different data rate and complexity.  When a FPGA logic registered to the Axi-Bus, it is memory mapped to the processor, and the processor can talk to it by writing to registers. 

    If you clarify what kind of data and how much data you want to transfer I can try to point you to the right direction.

    -Kevin

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    I want to send and receive a word that containts 64 letters. I would thank you if you were explaining to me how to do that or where i can read about that more in detail.

    And about my second question can i send data like one bit of data or somting like that from the C file to the pmod?

    thanks 

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  • Former Member
    0 Former Member over 11 years ago

    For sending one bit of data to pmod, there are a couple way of doing it.  One is enable PS's EMIO and use constraint to connect the pin to a PMOD port.  Check out Zedboard CTT (for Vivado 2013.2) chapter 3.  The example use EMIO to connect to a button for input; but you can change the IO pin to output and constrain it to a pmod pin instead.  To program the port, when you export to SDK the Xilinx tool will generate driver for EMIO, and you can take a look at that to see how to write data to the EMIO port.

    A second method is also shown in chapter 3, which is using a AXI-GPIO.  You can map the GPIO pin to any of the PMOD port, LED or button for input or output.  To write C program for it, similar to before Xilinx tool generate drivers and provide sample code.  AXI-GPIO is the method I have being using to send output pin signals.

    Anyway, take a look at CTT and let me know if you have question. Also, if you want to use I2C, SPI, or UART for sending/receiving data through pmod, it's actually pretty easy too.

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  • Former Member
    0 Former Member over 11 years ago

    The easiest method to pass data between PS and PL is again using an AXI-GPIO.  If you make the AXI-GPIO ports external and generate top level hdl, the port will show up on the interface, and you can connect those to your VHDL design.  When you use SDK, Xilinx tool will generate drivers for the AXI-GPIO access.  The drawback of this method is limited to transmitting 32 bit of data at a time, and you have to identify your own protocol for sending multiple characters.

    The other method is creating your own custom peripheral, and in that case you have the flexibility to use one of the three AXI interface. 

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  • Former Member
    0 Former Member over 11 years ago

    Also, check out this online tutorial:
    http://svenand.blogdrive.com/archive/175.html#.U4yzxx_welg

    It goes through the AXI GPIO method.

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    How can i use that from UART. I mean how can i send data through pmod by using UART.

    About the first quastion could you tell me after i do the ip design how i send data, i mean in what way through the terminal or what?
    i'd appreciate if you could tell me the steps about making my custom peripheral from the begining until the connection to my PC by terminal in general.

    thanks    

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  • Former Member
    0 Former Member over 11 years ago

    Thank you thchiou, this is very helpful!

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  • Former Member
    0 Former Member over 10 years ago

    Hi,
    We are using zedboard and we implement a uart IP core at pl side. we want to receive the data from ps side uart and same data wants to transmit over PL side uart.  How we can implment this.
    Thanks

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  • Former Member
    0 Former Member over 10 years ago in reply to Former Member

    As suggested above, an AXI interface is probably the best approach. You can add an AXI interface to your custom IP. Take a look at the Avnet Zynq Hardware Speedway tutorial for an example of how to create an AXI based custom IP:

     

    Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3 and 2014.4.1)

     

    or take a look at Jeff Johnson's tutorial:

     

    http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html

     

    or Adam Taylor's 7 part series on creating a PL peripheral starting here:

     

    https://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-One-Adam-Taylor-s-MicroZed-Chronicles-Part/ba-p/418935

     

    -Gary

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  • Former Member
    0 Former Member over 10 years ago

    I am following the online tutorial from the below link :

    https://forums.xilinx.com/xlnx/attachments/xlnx/ELINUX/8467/1/zedboard_CTT_v2013_2_130807.pdf

    I am trying to implement the setup given in the chapter 3 " embedded system design using zynq PS and PL". I am using vivado 2014.4, when when I try to modify the IP core as per their instructions , they show it has a MIO[53:0] port to which they are connecting MIO [53:0],they have shown a GPIO_I[0:0] on the zynq IP to which they connect "BTNR" and then gpio_io[0:0] theyt connect "BTNU". I am not able to implement any of these as I cannot add them on my Zynq IP,other remaining connections are well implemented.

    Is this because I am working on vivado 2014.4 which has zynq IP version of 5.5? Or am I missing something ?

    Any help will be appreciated !!

    Thanks,
    Raj

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