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ZedBoard Hardware Design Blink a LED only with Zynq FPGA(without using SDK)
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Related

Blink a LED only with Zynq FPGA(without using SDK)

Former Member
Former Member over 9 years ago

Hello,
I've followed the tutorials of section 1 and 4 in the Zynq Book Tutorials, they explained how to do a basic design on the ZedBoard and how to create an IP. The result of both tutorials was a LED that was blinking. However, both examples used the SDK and so the CPU of the ZedBoard.

I want to be able to design circuits only on the Zynq FPGA(without using the ARM processor). Can you please give me a tutorial/step by step explanation of how can I blink a LED on the ZedBoard when pressing a button by using only the CPU? I am using Vivado Web Edition, version 15.4.

Thank you!

PS:The VHDL code to do this would look like:
ENTITY part1 IS
PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); - - green LEDs
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
LEDG <= SW;
END Behavior
However, at which stage in Vivado should I do the pin assignation for example?

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  • Former Member
    0 Former Member over 9 years ago

    Hello guys,
    Thank you, finally I succeeded in programming the FPGA via the GUI of Vivado.

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    Hello Gary,
    Thank you for your answer.
    Can you please tell me which tutorial exactly shows how can I program the FPGA without using the SDK. I looked at the links and they all seem to be using the ARM CPU.

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  • Former Member
    0 Former Member over 9 years ago

    After you've done the above you should be able to do the same with the Vivado GUI. TroutChaser has given you some links to excellent tutorials.

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  • Former Member
    0 Former Member over 9 years ago

    If you would like to upload the bit-file (part1.bit) created by the script above you can save the following into program.tcl


    open_hw
    connect_hw_server -url TCP:localhost:3121
    set hw_target [get_hw_targets */xilinx_tcf/*]
    current_hw_target $hw_target
    set_property PARAM.FREQUENCY 6000000 $hw_target
    open_hw_target
    set fpga [lindex [get_hw_devices] 1]
    set_property PROGRAM.FILE part1.bit $fpga
    program_hw_devices $fpga
    exit

    Assuming the USB JTAG cable is connected to your Zedboard you should be able to load the bitfile using:

    vivado -mode tcl -source program.tcl

    After it has completed you should be able to flip the switches and watch the LED's change.

    If you have successfully done this you know that your hardware and toolchain is working correctly. Then you should try to go for some tutorials and other training.

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  • Former Member
    0 Former Member over 9 years ago

    Unless you want to use the JTAG interface to load your bitstream you will need at least a minimal Zynq PS block in your design to load the bitstream from the SD Card or QSPI Flash. There are quite a few tutorials on how to do this.

     

    The simplest are probably the MicroZed Tutorials, which should work for you if you just target the ZedBoard:

     

    http://zedboard.org/support/design/1519/10

     

    But it sounds like you could really benefit from a more complete training. Both the Zynq Software and Hardware Speedway workshops target the ZedBoard (or the MicroZed) and offer a much more in depth look at how the Zynq device and tools work:

     

    http://zedboard.org/support/trainings-and-videos

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago

    I followed a tutorial where it was explained how to create a project, how to add a vhdl and a constraint file to that project. However, I don't understand what should you do in vivado once you've created those two files? You generete the bitstream but after that what do you do to "put" the bitstream you've just generated on the Zynq FPGA?

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  • Former Member
    0 Former Member over 9 years ago

    The above *is* using Vivado, but in scripted mode. You simply save the two files, and then run the vivado command above. The result is a bit stream which will flash the corresponding led when you flip the switch.

    There are numerous tutorials on how to run the Vivado GUI to create a new project, select the Zedboard, add the vhdl file and do the pin assignments.


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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    Thank you for your answer.
    Is it possible instead of doing it on the Tcl command line to achieve the same result by using Vivado?
    If yes, can you explain me/give me a tutorial of how can I do that?

    Thanks!

    PS: Yes, I want to blink a led without using the CPU of the ZedBoard.

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    BTW: I assume you mean without the CPU in your message...

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  • Former Member
    0 Former Member over 9 years ago

    Create part1.vhd as:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;

    ENTITY part1 IS
      PORT ( SIGNAL SW   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
             SIGNAL LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); -- red LEDs
    END part1;

    ARCHITECTURE Behavior OF part1 IS
    BEGIN
      LEDG <= SW;
    END Behavior;

    Create compile.tcl as:

    create_project -in_memory -part xc7z020clg484-1
    read_vhdl part1.vhd
    synth_design -top part1 -part xc7z020clg484-1

    opt_design

    set_property PACKAGE_PIN T22 [get_ports {LEDG[0]}]
    set_property PACKAGE_PIN T21 [get_ports {LEDG[1]}]
    set_property PACKAGE_PIN U22 [get_ports {LEDG[2]}]
    set_property PACKAGE_PIN U21 [get_ports {LEDG[3]}]
    set_property PACKAGE_PIN V22 [get_ports {LEDG[4]}]
    set_property PACKAGE_PIN W22 [get_ports {LEDG[5]}]
    set_property PACKAGE_PIN U19 [get_ports {LEDG[6]}]
    set_property PACKAGE_PIN U14 [get_ports {LEDG[7]}]

    set_property IOSTANDARD "LVCMOS33" [get_ports {LEDG[*]}]

    set_property PACKAGE_PIN F22 [get_ports {SW[0]}]
    set_property PACKAGE_PIN G22 [get_ports {SW[1]}]
    set_property PACKAGE_PIN H22 [get_ports {SW[2]}]
    set_property PACKAGE_PIN F21 [get_ports {SW[3]}]
    set_property PACKAGE_PIN H19 [get_ports {SW[4]}]
    set_property PACKAGE_PIN H18 [get_ports {SW[5]}]
    set_property PACKAGE_PIN H17 [get_ports {SW[6]}]
    set_property PACKAGE_PIN M15 [get_ports {SW[7]}]
    set_property IOSTANDARD "LVCMOS18" [get_ports {SW[*]}]

    place_design
    phys_opt_design
    route_design

    set_property BITSTREAM.STARTUP.STARTUPCLK    JtagClk [current_design]
    set_property BITSTREAM.CONFIG.DCIUPDATEMODE  Quiet   [current_design]
    write_bitstream -verbose -mask_file -force part1.bit

    exit


    Then run:

    vivado -mode tcl -source compile.tcl

    You should now have a file called part1.bit which you can upload to your zedboard.

    Note that this script is known as non-project mode which is a bit unusual. I've left out parts like an xdc file (for timing) to make the example as simple as possible. You should be able to find tutorials on the net on how to use the GUI to do the same.

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