Hello,
I am trying to change the FCLK_CLK0 clock from 100 MHz to 200/250 MHz. This clock is connected to an AXI Interconnect, AXI CDMA and a template-generated peripheral (Default AXI Memory mapped). The issue is that my program works at 100 MHZ (I can create a DMA transfer from peripheral to DDR Mem) but at 200/250Mhz, the CDMA reports transfer error.
The issue seems to be that somehow, EDK is not imposing a timing constraint on my peripheral to work at that frequency. I am saying this because in PlanAhead Project Summary, in the Implemented Timing section it says "All constraints were met. Maximum Frequency: 100.291 Mhz", which is odd.
Investigating further, I have noticed there is a file, ./cryptozed.srcs/sources_1/edk/system/implementation/system_processing_system7_0_wrapper.ncf, which has the following lines:
############################################################################
# Clock constraints #
############################################################################
NET FCLK_CLK0 TNM_NET = clk_fpga_0;
TIMESPEC TS_clk_fpga_0 = PERIOD clk_fpga_0 100000 kHz;
I'm using PlanAhead 14.4.1
Any ideas?
I really appreciate any help you can provide,
Nicolae Rosia.
