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ZedBoard Hardware Design Implementing Vitis C code with Vivaod Verilog code
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  • zedboard
  • xilinx
  • vivado
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Related

Implementing Vitis C code with Vivaod Verilog code

CJK15
CJK15 over 1 year ago

I am currently using a PmodAD1 with code in Vitis as an ADC. The code reads the digital value obtained by the Pmod and writes it to the serial monitor. I intend to utilize this value to generate a PWM signal, with the duty cycle adjusting according to the input changes. The Pmod is currently operational, and I can generate a PWM signal in Verilog in separate projects. Modifying the duty cycle in the PWM Verilog code requires regenerating a bitstream and reprogramming the device each time. How can I integrate these components to have the PWM automatically update based on the Pmod's input? I am a student and would appreciate any advice. Thanks 

My block design:

image

My Verilog Code:
image

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  • javagoza
    javagoza over 1 year ago +2 verified
    I think you have at least two alternatives. The simplest is to use Vitis and make a program for the Zynq Processing System using the drivers provided by Digilent. Or you can complicate your life and create…
  • javagoza
    javagoza over 1 year ago +1
    This project in VHDL uses the PmodAD1. Active Power Meter Reference Project https://digilent.com/reference/basys/basys Active Power Meter reference design – zip file
  • CJK15
    CJK15 over 1 year ago in reply to javagoza +1
    I ended up keeping the project all in Vitis and it worked. Thanks for your help!
  • javagoza
    +1 javagoza over 1 year ago

    I think you have at least two alternatives. The simplest is to use Vitis and make a program for the Zynq Processing System using the drivers provided by Digilent. Or you can complicate your life and create an SPI driver in HDL to communicate with the PmodAD1. You can rely on the Digilent driver implementation. 

    https://github.com/Digilent/vivado-library/blob/master/ip/Pmods/PmodAD1_v1_0/src/ad1_spi.v

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  • javagoza
    0 javagoza over 1 year ago

    This project in VHDL uses the PmodAD1. Active Power Meter Reference Project

    https://digilent.com/reference/basys/basys

    • Active Power Meter reference design – zip file

    image

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  • CJK15
    0 CJK15 over 1 year ago in reply to javagoza

    I ended up keeping the project all in Vitis and it worked. Thanks for your help! 

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