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SSTL12 I/O standard compatible pins on Avnet ZUBoard 1CG

Niru_10

Hi,

I am using AVNET ZUBoard 1CG and trying to figure out the pins compatible with I/O standard SSTL12 and i found J6 supports the standard, but when i try in vivado .xdc file making a pin SSTL12, its throwing error at bitstream.
Please help me to find out the proper IO that supports SSTL12.

Below is the command i used.

set_property PACKAGE_PIN N3 [ct_out_0]
set_property IOSTANDARD SSTL12 [ct_out_0]

Thanks,

Nirupama.T

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  • 0

    Signals in HPIO banks like bank 65 and 66 can be setup to 1.2V.

    HDIO banks do not go that low voltage.

  • 0 in reply to iksevas

     
    I tried setting Bank 65 and 66 pins only, yet at the generate bitstream level, it throws error saying below

    [DRC NSTD-1] Unspecified I/O Standard: 1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ct_out_0.

    Can you help me with this?

    Regards,
    Nirupama.T

  • 0 in reply to Niru_10

    This error message tells you the port CT_OUT_0 of your design does not have an IOSTANDARD defined (even though I see your XDC constraint in this thread). There would be no way for me to provide guidance on this without having access to your design. Problem with that is that I may not have the tool version you are working on. 

    I see you are targeting a bank 65 pin single-ended to the PL HSIO connector, so this is a correct mapping of a 1.2V standard to a pin. I see that you can jumper select 1.2V as the voltage for that bank on the ZUBoard/

    There has to be something simple in your design that is being missed. 

  • 0 in reply to iksevas

     

    The below is my design, where I'm taking default configuration of zynq ultrascale+MPSoc and connected it to clocking wizard and generated two clocks of 200 and 800 MHz each and the 200 MHz clock is provided as source to counter and the output of counter is the CT_OUT_0.

    Below is my design. and the default jumper setting is 1.2v, Anyways the design is failing at bitstream phase, so didn't go till board level execution.

    image

  • 0 in reply to Niru_10

    You appear to be entering the constraints incorrectly. I created an example design with the following constraints:

    set_property PACKAGE_PIN N3 [get_ports {CT_OUT_0[0]}]
    set_property IOSTANDARD SSTL12 [get_ports {CT_OUT_0[0]}]

    Also with the following block design:

    image

    I had no issue getting to a final solution. Please revisit your constraints.

    Here is the IO report:

    image

  • 0 in reply to iksevas

    Potentially, your XDC file (syntax) is wrong. I can use properly pins as LVCMOS12 on this header (as the IO Standard).

    Are you sure SSTL12 is the right declartion for simple 1V2 pins (used just for DDR memory pins with a ref. voltage as well, VREF an VTT)?

    Try LVCMOS12 instead...

  • 0 in reply to iksevas

     

    This works now, I'm not sure what is the issue earlier, Maybe its the constraints not properly added.


    Thanks,

    Nirupama.T

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