I mentioned in a previous post that we were investigating a cold start issue on some Avnet products related to a spec change to the IRPS5401 PMIC from Infineon. To learn more about the issue please check out my previous blog - /technologies/power-management/b/blog/posts/irps5401-pmic-cold-start-spec-change
This issue only presents itself at -40C, which means it only affects the industrial temp Ultra96-V2, UltraZed EG and EV SOMs. The commercial temp grade SOMs and carriers do not have the issue, however we do use the same PCB for both varieties so in the case of the UltraZed SOMs, a board spin was required. I have attached a zip file to this blog that contains both ECN documents for the EV and EG SOMs.
The simple explanation is that a timing change was needed at cold temp. On the Ultra96-V2, we had extra time available to slow down the supply startups to meet the requirement. On the UltraZed platforms we implement the sequencing using timing delays from startup. Because of this sequencing / timing architecture, we did not have enough time left to delay the start up sequence long enough to meet the new requirement. There is a maximum time delay limit for startup from "enable", while we had margin to work with on Ultra96-V2, since the UltraZed platform has more rails as well as a carrier that require additional timing delays, the only way to meet the new timing requirement and not violate maximum delay constraints was to add an RC delay to the initial startup signal. Please review the attached ECNs, if you have any questions or concerns please don't hesitate to comment or reach out and I can provide more details.
Thanks
Chris
