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PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design

Jan Cumps

I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.

Register the IP and Use it in Vivado

In part 1, we made the hardware accelerated function example(stream &in, stream &out). Our next step is to build a Vivado hardware design.
It will include this accelerated IP, and the FPGA blocks before and after it to interface between the ARM controllers and the IP via AXI, memory maps and DMA.
If you follow the tutorial step by step, it's not hard.

image

image: add the accelerator example IP to the project's IP repository

Once you create the project, you can register the IP. You can then add it to your block design.

image

image: add the IP to your block design

The remainder of the exercise is to add the ARM block, reset, interrupt handler, DMA harness.
Most of these have been reviewed in the blog series. I'll show the DMA part.

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image: block design with the accelerator IP surrounded by DMA and memory map blocks

The DMA data width to and from the IP is set to 32 bits. 

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image: DMA settings

You'll see three AXI Interconnect blocks. One at the left and two at the right side.
The left one is an AXI Lite block, where non-DMA control messages are exchanged with the ARM. This is for any info, except the input- and output data streams.
The IP streams are connected to the DMA block's streaming pipelines. The other sides of the DMA pipelines are connected via the remaining two AXI Interconnects to and from the ARM memory. 

image

image: AXI Lite control of the accelerator IP (red) and the high-speed DMA input and output streams (orange)

Memory Map Addresses

The DMA section shows the memory area for input and output data, using high performance channels.
The section underneath that shows the normal performance channels used for controlling DMA and Accelerator IP.

image

You can collect the design implementation files that need to be uploaded to the PYNQ board using the script I created for that.

Next post, this design gets loaded and we'll execute the hardware accelerated function from software.

 

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Learning Xilinx Zynq: Hardware Accelerated Software
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Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
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PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse