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Just a headsup that the low-end dev kit "XMOS - XK-1A (KIT) - XS1-L8-64, 400MIPS, 8CORE, DEV KIT" (£59.00) at Farnell UK links to an old version of the XK-1A Hardware Manual that describes a kit employing the single-core XMOS XS1-L01A-TQ128 device, not the 8-core XS1-L8A-64-TQ128 device advertised. The old manual doesn't seem to have an updated version anywhere, not even at XMOS.
Good to see that they upgraded the kit, as a single core wouldn't have provided much of an evaluation of this multi-core family.
So, which of you OSHW front-runners is mounting a £25.56 XS1-L16A-128-QF124-C10 (16 CORE, 1000MIPS) device on a breakout board for us? 
(This video from over a year ago shows that breakouts/DIP-headers have already been in the making.)
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Addendum (important): It seems likely that the devices have been renamed rather than that the XK-1A kit was upgraded.
The XS1-L8A-64-TQ128 datasheet describes the device as having a single tile with 8 logical cores, and in only one place is a thread number mentioned (page 32) in reference to a resource ID of a logical core --- apparently that single occurrence escaped the global edit. This contrasts with references to single core with 8 hardware threads (plus a thread scheduler with separate registers per thread) that I've seen elsewhere. It seems that Marketing did a bit of a job on it.
XMOS's architectural documentation lends weight to the renaming --- "The XMOS XS1 Architecture (ISA)" book says that "Each XCore has hardware support for executing a number of concurrent threads", whereas the newer "xCORE Architecture Introduction" says that "The xCORE multicore microcontroller is made up from multiple `logical proc essor cores' distributed across Tiles . Devices are currently available with 4, 6, 8, 10, 12, 16 and 32 logical cores on 1, 2 and 4 tiles."
If this conclusion is incorrect and XS1-L8A-64-TQ128 does actually have 8 cores each of which runs 8 threads, please let me know. There's an "-64" in the name that I haven't fully been able to account for yet (but it's almost certainly memory size, 64KB vs 128KB), so it's possible. (Once I know which is correct, I'll zap the wrong interpretation here to avoid confusing anyone else.)
(The renaming now seems a certainty. There's even a section in the docs page called "Previous Part Marking" listing the XS1-L01A-* devices.)
Just a headsup that the low-end dev kit "XMOS - XK-1A (KIT) - XS1-L8-64, 400MIPS, 8CORE, DEV KIT" (£59.00) at Farnell UK links to an old version of the XK-1A Hardware Manual that describes a kit employing the single-core XMOS XS1-L01A-TQ128 device, not the 8-core XS1-L8A-64-TQ128 device advertised. The old manual doesn't seem to have an updated version anywhere, not even at XMOS.
Good to see that they upgraded the kit, as a single core wouldn't have provided much of an evaluation of this multi-core family.
So, which of you OSHW front-runners is mounting a £25.56 XS1-L16A-128-QF124-C10 (16 CORE, 1000MIPS) device on a breakout board for us? (This video from over a year ago shows that breakouts/DIP-headers have already been in the making.)
===
Addendum (important): It seems likely that the devices have been renamed rather than that the XK-1A kit was upgraded.
The XS1-L8A-64-TQ128 datasheet describes the device as having a single tile with 8 logical cores, and in only one place is a thread number mentioned (page 32) in reference to a resource ID of a logical core --- apparently that single occurrence escaped the global edit. This contrasts with references to single core with 8 hardware threads (plus a thread scheduler with separate registers per thread) that I've seen elsewhere. It seems that Marketing did a bit of a job on it.
XMOS's architectural documentation lends weight to the renaming --- "The XMOS XS1 Architecture (ISA)" book says that "Each XCore has hardware support for executing a number of concurrent threads", whereas the newer "xCORE Architecture Introduction" says that "The xCORE multicore microcontroller is made up from multiple `logical proc essor cores' distributed across Tiles . Devices are currently available with 4, 6, 8, 10, 12, 16 and 32 logical cores on 1, 2 and 4 tiles."
If this conclusion is incorrect and XS1-L8A-64-TQ128 does actually have 8 cores each of which runs 8 threads, please let me know. There's an "-64" in the name that I haven't fully been able to account for yet (but it's almost certainly memory size, 64KB vs 128KB), so it's possible. (Once I know which is correct, I'll zap the wrong interpretation here to avoid confusing anyone else.)
(The renaming now seems a certainty. There's even a section in the docs page called "Previous Part Marking" listing the XS1-L01A-* devices.)
