Free Developement tools from XMOS

A short rummage around the Xcore site lead me to The XCore Open Source Project and the Xcore Github repo, which as an open source advocate, I found very encouraging.  I also noted the contributor's agreement  which goes beyond forking Github repos and allows developers to contribute more directly back to the company sources.  I see this as a sign that open source interest at Xcore is rather more substantial than the "throw code over the wall" kind of openness which is unfortunately common.

Which leads me to a couple of questions:

1. Is the impression I've gained above correct?
2. Are XMOS devices fully documented so that OSHW communities can develop around these devices and create their own complete toolchains to program them?

Question 2 relates to the uncomfortable situation we presently have with FPGA manufacturers, none of which provide complete programming information for their devices so that it has been impossible for the community to develop full toolchains for them.  This has effectively extinguished open source progress in that area.

If the answer is "Yes" to both questions then this is going to be of interest to many.

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Addendum:  I had asked about unit availability earlier too, but the answer was right here at Farnell UK, 6 different devices all in stock!  Excellent!

I hadn't realized Farnell stock XMOS but they do, which is great. I've never had a chance to look into it, but for many years they've had some reasonably priced demo kits, a nice range of parts and also they maintain a great library of code for different use-cases. They're based in the UK. From a quick look their documentation looks ok (not outstandingly spectacular 1000-page volumes like Freescale or TI - that would be a hard thing to exceed) but it looked good enough. Very interesting :-)

shabaz wrote:

 

I hadn't realized Farnell stock XMOS but they do, which is great. I've never had a chance to look into it, but for many years they've had some reasonably priced demo kits, a nice range of parts and also they maintain a great library of code for different use-cases. They're based in the UK. From a quick look their documentation looks ok (not outstandingly spectacular 1000-page volumes like Freescale or TI - that would be a hard thing to exceed) but it looked good enough. Very interesting :-)

I'm not impressed by 1000-page tomes (4593 pages for TI's "AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual" rev C).  I like well-organized shorter manuals written by people who actually print hard copy every now and then.  We had shorter manuals when the vendors gave away hard copies

I think when you are paying for the paper the urge to "cut and Paste" is MUCH less

The Documentation for the XMOS stufff is normally clear and short, I have found the tech support

to be very useful as well.

All and all the hardrealtime of the XMOS potentially saves a load of brain ache as an alternative

to an FPGA solution!

I had mentioned to some Farnell guys about getting these devices but i never noticed them "arrive" thanks for pointing it out ..Should be easier than getting them from places I probably shouldnt mention

Morgane they contributed quite heavily at one point to the OSHUG guys and attended several of their meetings that I unfortunately missed

There are several guys doing some 3D printer stuff using the XMOS rather than Arduinos.

Also I've found the content of the Xcore site to be very good .. my only issue was the number of parked or stale projects that I spotted  as I was looking for similar stuff that I was doing at the time.

John Alexander wrote:

 

Morgane they contributed quite heavily at one point to the OSHUG guys and attended several of their meetings that I unfortunately missed

I noticed the XMOS talk listed on the OSHUG event calendar, but when I looked on Youtube earlier today I couldn't find a video of that presentation.  I'll look deeper tomorrow.

I've been examining technical details of the XMOS architecture in the last few hours and I'm getting excited --- this device family really is a pretty close descendant of the transputer, as claimed!  For anyone with background in that golden age of parallelism "done right", all I/we can say is "It's about time!!!".  The transputer was so far ahead of what anyone else was doing with parallelism in the 80's that it probably fell out of the Tardis.

It's no surprise that XMOS is so strongly related to the transputer of course, since David May is the XMOS CTO.  He has many interesting documents and presentations on his personal website, worth checking out.

Multiple cores, inter-core links on-chip and between chips, hardware thread scheduler ... this is where we should have been for the last 40 years.  I hope it takes off and remains this time, and we don't have to wait yet another 40.

Regarding my questions, the sense I'm getting from the technical documentation is that these devices are completely open.  Hopefully XMOS Support will confirm my question #2 some time, but so far I'm very hopeful that these are devices that the OSHW + FOSS community can support fully.

And finally I'll end with a beautiful quote from David May, unrelated to XMOS but exactly reflecting what lots of us have said in various threads:

David may wrote:

 

"Software efficiency halves every 18 months, compensating for Moore's Law."

So true.  

Just a headsup that the low-end dev kit "XMOS - XK-1A (KIT) - XS1-L8-64, 400MIPS, 8CORE, DEV KIT" (£59.00) at Farnell UK links to an old version of the XK-1A Hardware Manual  that describes a kit employing the single-core XMOS XS1-L01A-TQ128 device, not the 8-core XS1-L8A-64-TQ128 device advertised.  The old manual doesn't seem to have an updated version anywhere, not even at XMOS.

Good to see that they upgraded the kit, as a single core wouldn't have provided much of an evaluation of this multi-core family.

So, which of you OSHW front-runners is mounting a £25.56 XS1-L16A-128-QF124-C10 (16 CORE, 1000MIPS) device on a breakout board for us?   (This video from over a year ago  shows that breakouts/DIP-headers have already been in the making.)

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Addendum (important):  It seems likely that the devices have been renamed  rather than that the XK-1A kit was upgraded.

The XS1-L8A-64-TQ128 datasheet describes the device as having a single tile with 8 logical cores, and in only one place is a thread number mentioned (page 32) in reference to a resource ID of a logical core --- apparently that single occurrence escaped the global edit.  This contrasts with references to single core with 8 hardware threads (plus a thread scheduler with separate registers per thread) that I've seen elsewhere.  It seems that Marketing did a bit of a job on it.

XMOS's architectural documentation lends weight to the renaming --- "The XMOS XS1 Architecture (ISA)" book says that "Each XCore has hardware support for executing a number of concurrent threads", whereas the newer "xCORE Architecture Introduction" says that "The xCORE multicore microcontroller is made up from multiple `logical proc essor cores' distributed across Tiles . Devices are currently available with 4, 6, 8, 10, 12, 16 and 32 logical cores on 1, 2 and 4 tiles."

If this conclusion is incorrect and XS1-L8A-64-TQ128 does actually have 8 cores each of which runs 8 threads, please let me know.  There's an "-64" in the name that I haven't fully been able to account for yet (but it's almost certainly memory size, 64KB vs 128KB), so it's possible.  (Once I know which is correct, I'll zap the wrong interpretation here to avoid confusing anyone else.)

(The renaming now seems a certainty.  There's even a section in the docs page called "Previous Part Marking" listing the XS1-L01A-* devices.)

Are XMOS devices fully documented so that OSHW communities can develop around these devices and create their own complete toolchains to program them?

We do have public documentation for enough stuff (architecture, ABI etc.) to create a toolchain. Have a look at the following projects for more details:

http://www.xcore.com/projects/gcc-xs1
http://www.xcore.com/projects/binutils-xs1

Ha yes agreed, thanks for the link to David's site.

For the longest time they were more accurate about the Cores thing i.e. your single CPU would have up to 8 threads and a hard realtime scheduler.

You could have up to 4 real CPUs on each Package giving you 32 threads.

However with every one gone core crazy they felt it better marketting to call each context a core so all of a sudden your chips can suppport 8-32 cores remember bigger is better