The P4080DS is a flexible development system supporting NXP’s P4080, P4040 and P4081 processors. The board, with its rich I/O mix, is intended for initial target development and evaluation of P4080 and P4040 processors.

The P4080DS can help shorten your time to market. The board, which exercises most capabilities of the device, can serve as a reference for hardware development. It can also be used as a debug tool to check behaviors on the board compared to behaviors seen on customer boards. It can be used for software development and performance evaluation before the custom board is ready.

The P4080 processor is based upon the e500mc core, built on Power Architecture technology, offering speeds of 1200–1500 MHz. It has a three-level cache hierarchy with 32 KB of instruction and data cache per core, 128 KB of unified backside L2 cache per core and 2 MB of shared frontside CoreNet platform cache that fronts the memory controller. The processor’s I/O includes 18 SerDes lanes running at up to 5 GHz, multiplexed across three PCI Express Gen2 controllers, two 10 GE XAUI interface, eight 1 GE SGMII interfaces, two Serial RapidIO 1.2 interfaces running at up to 3.125 GHz, and the high-speed Aurora debug interface. It has a dual 64-bit (72-bit with ECC) DDR2 and DDR3 DRAM interfaces running at up to 1333 MHz. It includes two USB 2.0 interfaces (with ULPI interface to external PHY), two DUARTs, an SD/MMC interface, four I 2 C, and SPI. It also includes the accelerator blocks collectively known as Data Path Acceleration Architecture (DPAA) that offload various tasks from the core, including routine packet handling, security algorithm calculation and pattern matching. 

Applications:

• Industrial
  • Ethernet Switch 
• Networking
  • Unified Threat Management (UTM)
  • Macrocell Base Station
  • Router