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How to change dtsi(eg:maaxboard-extended-gpio.dtsi)  to make M41T93 spi rtc work in maaxboard yocto zeus branch?

gonewtinwind

Hi Josh,

I use maaxboard board (not mini, not nano)

the M41T93 spi rtc works well in kernel 4.14(yocto sumo branch) , I showed here before: Enable the SPI port on MaaxBoard?

but

I need to add M41T93 spi rtc chip in yocto zeus branch(kernel 5.4),but I find the maaxboard-extended-gpio.dtsi  is different with maaxboard-nano-extended-gpio.dtsi.

the maaxboard-extended-gpio.dtsi file still keeps the gpio for  old settings , I thought the zeus did not support maaxboard now, so I need to modify it similar to  maaxboard-nano-extended-gpio.dtsi.

so I change the ecspi part as the below  patch file(see attached file,001-spi-real-time-M41T93.patch, I change kernel config,I can find the /dev/rtc0, I removed snvs_rtc),but unfortunately the spi rtc still not work!

How to change the dtsi in kerenel 5.4? I think maaxboard nano work well, I just follow it to modify maaxboard .dtsi file  similiarly . the spi rtc should work.

Thank you very much.

 

 

my full patch file:

 

diff -Naur ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi

--- ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi       2021-04-15 12:55:28.039009295 -0400

+++ patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi   2021-04-15 16:33:48.243133485 -0400

@@ -591,15 +591,6 @@

                                compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";

                                reg = <0x30370000 0x10000>;

 

-                               snvs_rtc: snvs-rtc-lp{

-                                       compatible = "fsl,sec-v4.0-mon-rtc-lp";

-                                       regmap =<&snvs>;

-                                       offset = <0x34>;

-                                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

-                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

-                                       clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;

-                                       clock-names = "snvs-rtc";

-                               };

 

                                snvs_pwrkey: snvs-powerkey {

                                        compatible = "fsl,sec-v4.0-pwrkey";

@@ -832,7 +823,7 @@

                                clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,

                                         <&clk IMX8MQ_CLK_ECSPI1_ROOT>;

                                clock-names = "ipg", "per";

-                               status = "disabled";

+                               status = "enabled";

                        };

 

                        ecspi2: spi@30830000 {

diff -Naur ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi

--- ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi      2021-04-08 14:58:09.820015901 -0400

+++ patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi  2021-04-19 13:57:18.993139208 -0400

@@ -37,10 +37,15 @@

 

                pinctrl_ecspi1: ecspi1grp {

                                fsl,pins = <

-                               MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x16

-                               MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x16

-                               MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x16

-                               MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x1816

+                               MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82

+                               MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82

+                               MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82

+                       >;

+               };

+

+               pinctrl_ecspi1_cs: ecspi1cs {

+                       fsl,pins = <

+                               MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40000

                        >;

                };

 

@@ -90,10 +95,19 @@

 

&ecspi1{

        fsl,spi-num-chipselects = < 1 >;

-       cs-gpios = <&gpio5 13 0 > ;

+       cs-gpios = <&gpio5 9 0 > ;

        pinctrl-names = "default";

-       pinctrl-0 = <&pinctrl_ecspi1 >;

+       pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;

        status = "okay";

+       #address-cells=<1>;

+       #size-cells=<0>;

+       rtc@0x00{

+       #address-cellss=<1>;

+       #size-cells=<1>;

+       compatible = "rtc-m41t93";

+       spi-max-frequency = <5000000>;

+       reg = <0>;

+    };

};

 

&i2c2 {

                                                                                                                                                                                                                          73,1          Bot

Attachments:
001-spi-real-time-M41T93.txt.zip
Parents

  • maaxboard login: root                                                          

    Password:                                                                      

    Last login: Wed Apr  7 13:21:56 UTC 2021 on tty7                               

    root@maaxboard:~# hwclock -r                                                   

    [   71.287904] rtc rtc0: __rtc_set_alarm: err=-22                              

    hwclock: select() to /dev/rtc0 to wait for clock tick timed out                

    root@maaxboard:~# dmesg | grep rtc                                             

    [    1.707508] rtc-m41t93 spi0.0: registered as rtc0                           

    [    3.165010] rtc-m41t93 spi0.0: hctosys: unable to read the hardware clock   

    [   71.287904] rtc rtc0: __rtc_set_alarm: err=-22                              

    root@maaxboard:~# dmesg | grep rtc                                             

    [    1.707508] rtc-m41t93 spi0.0: registered as rtc0                           

    [    3.165010] rtc-m41t93 spi0.0: hctosys: unable to read the hardware clock   

    [   71.287904] rtc rtc0: __rtc_set_alarm: err=-22        

  • in reply to gonewtinwind

    I think there are some errors in dtb source code,but I can not find where it is.

    any help?

Reply Children
  • in reply to gonewtinwind

    Hi peter,

     

    I am looking into this. Will hopefully have an answer for you tomorrow.


    Thanks,
    Josh

  • in reply to jafoste4

    Thank you. I think the issue maybe at there: (tested,still not work)

    -                               MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x16

    -                               MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x16

    -                               MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x16

    -                               MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x1816

     

     

     

     

    I cat  ./imx8mq-zii-ultra-rmb3.dts.

    it is:

     

     

     

    &iomuxc {

      pinctrl_ecspi1: ecspi1grp {

      fsl,pins = <

      MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19

      MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82

      MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82

      MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82

      >;

      };

    };

     

     

     

    I am trying to fix it.

    sorry, I tried, but still not work.

    the patch file:

     

     

    diff -Naur ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi

    --- ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi       2021-04-15 12:55:28.039009295 -0400

    +++ patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi   2021-04-22 17:38:26.638367400 -0400

    @@ -591,15 +591,6 @@

                                    compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";

                                    reg = <0x30370000 0x10000>;

     

    -                               snvs_rtc: snvs-rtc-lp{

    -                                       compatible = "fsl,sec-v4.0-mon-rtc-lp";

    -                                       regmap =<&snvs>;

    -                                       offset = <0x34>;

    -                                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

    -                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

    -                                       clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;

    -                                       clock-names = "snvs-rtc";

    -                               };

     

                                    snvs_pwrkey: snvs-powerkey {

                                            compatible = "fsl,sec-v4.0-pwrkey";

    @@ -832,7 +823,7 @@

                                    clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,

                                             <&clk IMX8MQ_CLK_ECSPI1_ROOT>;

                                    clock-names = "ipg", "per";

    -                               status = "disabled";

    +                               status = "enabled";

                            };

     

                            ecspi2: spi@30830000 {

    diff -Naur ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi

    --- ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi      2021-04-08 14:58:09.820015901 -0400

    +++ patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi  2021-04-22 18:02:45.309302120 -0400

    @@ -37,10 +37,10 @@

     

                    pinctrl_ecspi1: ecspi1grp {

                                    fsl,pins = <

    -                               MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x16

    -                               MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x16

    -                               MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x16

    -                               MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x1816

    +                               MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x19

    +                               MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82

    +                               MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82

    +                               MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82

                            >;

                    };

     

    @@ -89,11 +89,17 @@

    };

     

    &ecspi1{

    -       fsl,spi-num-chipselects = < 1 >;

    -       cs-gpios = <&gpio5 13 0 > ;

    -       pinctrl-names = "default";

    -       pinctrl-0 = <&pinctrl_ecspi1 >;

    -       status = "okay";

    +        fsl,spi-num-chipselects = < 1 >;

    +        pinctrl-names = "default";

    +        pinctrl-0 = <&pinctrl_ecspi1 >;

    +        cs-gpios = <&gpio5 9 0 > ;

    +        status = "okay";

    +

    +        rtc@0x00{

    +                compatible = "rtc-m41t93";

    +                spi-max-frequency = <5000000>;

    +                reg = <0>;

    +        };

    };

     

    &i2c2 {

                                                                                                                                                                                                                              69,1          Bot

                                                                                                                                                                                                                             1,1           Top

  • in reply to gonewtinwind

    Hi Peter,

     

    I am having an issue uploading a diff file to E14, I will email it to you directly. This diff that we made based on the latest linux source code(commit: 49174803839815089d7c6c42631e415260778b4f at branch: maaxboard_5.4.24_2.1.0 ) according to your needs. Unfortunatly we don’t have such a SPI RTC device to try, please give it a try and let me know.

     

    Thanks,
    Josh

  • in reply to jafoste4

    it still not work. I think the pin value settings are wrong. or spi deep driver not work.

     

     

    my patch:

     

    diff -Naur ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi

    --- ori/arch/arm64/boot/dts/freescale/imx8mq.dtsi 2021-04-15 12:55:28.039009295 -0400

    +++ patches/arch/arm64/boot/dts/freescale/imx8mq.dtsi 2021-04-26 10:04:51.780796943 -0400

    @@ -832,7 +832,7 @@

      clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,

      <&clk IMX8MQ_CLK_ECSPI1_ROOT>;

      clock-names = "ipg", "per";

    - status = "disabled";

    + status = "enabled";

      };

     

      ecspi2: spi@30830000 {

    diff -Naur ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi

    --- ori/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi 2021-04-08 14:58:09.820015901 -0400

    +++ patches/arch/arm64/boot/dts/freescale/maaxboard-extended-gpio.dtsi 2021-04-26 10:08:59.210155738 -0400

    @@ -37,10 +37,10 @@

     

      pinctrl_ecspi1: ecspi1grp {

      fsl,pins = <

    - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x16

    - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x16

    - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x16

    - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1816

    + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19

    + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82

    + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82

    + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82

      >;

      };

     

    @@ -89,13 +89,24 @@

    };

     

    &ecspi1{

    - fsl,spi-num-chipselects = < 1 >;

    - cs-gpios = <&gpio5 13 0 > ;

    - pinctrl-names = "default";

    - pinctrl-0 = <&pinctrl_ecspi1 >;

    - status = "okay";

    +        fsl,spi-num-chipselects = < 1 >;

    +        pinctrl-names = "default";

    +        pinctrl-0 = <&pinctrl_ecspi1 >;

    +        cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH >;

    +        status = "okay";

    +       #address-cells = <1>;

    +       #size-cells = <0>;

    +        rtc@0{

    +                compatible = "rtc-m41t93";

    +                spi-max-frequency = <5000000>;

    +                reg = <0>;

    +        };

    };

     

    +&snvs_rtc {

    +       status = "disabled";

    + };

    +

    &i2c2 {

      clock-frequency = <400000>;

      pinctrl-names = "default";

  • in reply to gonewtinwind

    Maybe  I need to remove line :   fsl,spi-num-chipselects = < 1 >;   let me test

    ----

    sorry, not work!

    tomorrow I will use the scope to test the signals