Parallella $99 board now open hardware on Github

Morgaine Dinova wrote:

 

The 16-core board is priced at US$99 and its host ARM is a dual-core Cortex-A9 (Xilinx Zynq 7010 or 7020).  It comes with 1GB DDR3, host and client USB, native gigabit Ethernet and HDMI, so at that price this would be a fairly interesting board even without its 16-core Epiphany coprocessor. 

I've wondered about these for a while.. 16 or 64 cores of a specialised processor that probably can't run linux or other general purpose OS makes it highly niche.  If they sell many of these, I seriously wonder how many will get used as a dual core Arm with the Ephiphany sitting idle.

Bitcoin miner perhaps ?

selsinork wrote:

 

I've wondered about these for a while.. 16 or 64 cores of a specialised processor that probably can't run linux or other general purpose OS makes it highly niche.  If they sell many of these, I seriously wonder how many will get used as a dual core Arm with the Ephiphany sitting idle.

Kind of like a BBB used for its single-core ARM while its 2 PRUs are sitting idle, except there's 16 of them?

The Epiphany cores seem a lot more capable than PRUs though.  They're clocked at 1GHz, and they each have 1MB of local RAM address space (only partly populated with 32KB per core on the current generation 16 and 64-core devices) as well as slower indirect access to all other cores' memory spaces.

From http://www.adapteva.com/products/silicon-devices/e16g301/ :

 

RISC Processor:
Each compute node contains an independent superscalar floating-point RISC CPU operating at 1 GHz and 2 GFLOPS/sec. The CPU has an efficient general-purpose instruction set that excels at compute intensive applications while being efficiently programmable in C/C++ without any need to write code using assembly or processor specific intrinsics.

Memory System:
The Epiphany memory architecture is based on a flat memory map in which each compute node has a small amount of local memory as a unique addressable slice of the total 32-bit address space. A processor can access its own local memory and other processors memory through regular load/store instructions, with the only difference being the latency and effective throughput of the transactions. The local memory system is comprised of 4 separate banks, allowing for simultaneous memory access by the instruction fetch engine, local load-store instructions, and by load/store transactions initiated by other processors within system.

 

Network-On-Chip:
The eMesh Network-on-Chip is a 2D mesh network that handles all on-chip ad off-chip communication. The network is based on atomic 32- bit memory transactions and is transparent to the program running. The network consists of three separate and orthogonal mesh structures, each serving different types of transaction traffic: one network for on-chip write traffic, one network for off chip write traffic, and one network for all read traffic.

Off-Chip IO:
The eMesh network and memory architecture is extended off-chip using source synchronous LVDS based serial links that provide up to 2GB/sec of effective bandwidth per link. Each E16G301 has 4 links, one in each direction (north, east, west, south), allowing chips to be easily interfaced with FPGAs and/or other E16G301 chips on a board.

I don't know whether the last paragraph means that the Zynq's FPGA has been configured to extend Epiphany core non-local bus access all the way into host memory space.  That would be pretty complex, maybe requiring a split transaction bus or at least some kind of queueing, and of course the contention would be horrible if all cores were to access the host concurrently.  Perhaps there is some kind of core-to-host signaling at least though.

The "4 links, one in each direction (north, east, west, south)" immediately spells "transputer" to us old timers.

Of course, Epiphany cores being programmable in C/C++ is the key feature that will make all the difference in practice.  Here's a video from a year ago demonstrating the same matrix code running on a 64-core Epiphany in 220 ms and on some kind of x86 PC in 4591 ms, while consuming only around 2W.  It suggests that a lot of people are going to like this board.

I'm really looking forward to it becoming generally available.

selsinork wrote:

 

I've wondered about these for a while.. 16 or 64 cores of a specialised processor that probably can't run linux or other general purpose OS makes it highly niche.  If they sell many of these, I seriously wonder how many will get used as a dual core Arm with the Ephiphany sitting idle.

Kind of like a BBB used for its single-core ARM while its 2 PRUs are sitting idle, except there's 16 of them?

The Epiphany cores seem a lot more capable than PRUs though.  They're clocked at 1GHz, and they each have 1MB of local RAM address space (only partly populated with 32KB per core on the current generation 16 and 64-core devices) as well as slower indirect access to all other cores' memory spaces.

From http://www.adapteva.com/products/silicon-devices/e16g301/ :

 

RISC Processor:
Each compute node contains an independent superscalar floating-point RISC CPU operating at 1 GHz and 2 GFLOPS/sec. The CPU has an efficient general-purpose instruction set that excels at compute intensive applications while being efficiently programmable in C/C++ without any need to write code using assembly or processor specific intrinsics.

Memory System:
The Epiphany memory architecture is based on a flat memory map in which each compute node has a small amount of local memory as a unique addressable slice of the total 32-bit address space. A processor can access its own local memory and other processors memory through regular load/store instructions, with the only difference being the latency and effective throughput of the transactions. The local memory system is comprised of 4 separate banks, allowing for simultaneous memory access by the instruction fetch engine, local load-store instructions, and by load/store transactions initiated by other processors within system.

 

Network-On-Chip:
The eMesh Network-on-Chip is a 2D mesh network that handles all on-chip ad off-chip communication. The network is based on atomic 32- bit memory transactions and is transparent to the program running. The network consists of three separate and orthogonal mesh structures, each serving different types of transaction traffic: one network for on-chip write traffic, one network for off chip write traffic, and one network for all read traffic.

Off-Chip IO:
The eMesh network and memory architecture is extended off-chip using source synchronous LVDS based serial links that provide up to 2GB/sec of effective bandwidth per link. Each E16G301 has 4 links, one in each direction (north, east, west, south), allowing chips to be easily interfaced with FPGAs and/or other E16G301 chips on a board.

I don't know whether the last paragraph means that the Zynq's FPGA has been configured to extend Epiphany core non-local bus access all the way into host memory space.  That would be pretty complex, maybe requiring a split transaction bus or at least some kind of queueing, and of course the contention would be horrible if all cores were to access the host concurrently.  Perhaps there is some kind of core-to-host signaling at least though.

The "4 links, one in each direction (north, east, west, south)" immediately spells "transputer" to us old timers.

Of course, Epiphany cores being programmable in C/C++ is the key feature that will make all the difference in practice.  Here's a video from a year ago demonstrating the same matrix code running on a 64-core Epiphany in 220 ms and on some kind of x86 PC in 4591 ms, while consuming only around 2W.  It suggests that a lot of people are going to like this board.

I'm really looking forward to it becoming generally available.

Morgaine Dinova wrote:

 

Of course, Epiphany cores being programmable in C/C++ is the key feature that will make all the difference in practice.

Maybe, but one thing that's become clear from the RPi phenomena is that the majority of people just want a cheap media player and don't care what else it might be capable of.

For the 16 or 64 cores to get used they need some practical purpose that's generally useful to more than a demo or niche application. Otherwise, just on the Arm cores alone, how does it compare to one of those A20 OLinuxino's ?

On ARM performance:

selsinork wrote:

 

Otherwise, just on the Arm cores alone, how does it compare to one of those A20 OLinuxino's ?

Probably not quite as good, since the OLinuXino's A20 runs at 1GHz instead of the 800MHz of the Parallella's Zynq, and the A20 features the more modern Cortex-A7 MPcore whereas Zynq 7010/7020 uses the older Cortex-A9 MPcore.  Both are dual core, but the A20 OLinuXino can be expected to have the edge on pure ARM SoC performance.  Of course, the Parallella would trounce OLinuXino totally if the Epiphany can be brought into play as an accelerator, but that's a hope rather than an actuality.

Also, the A20 OLinuXino will provide SATA which Parallella lacks, whereas Parallella provides gigabit Ethernet which the currently specified A20 OLinuXino boards lack despite the A20 having gigabit capability.  That suggests that the A20 OLinuXino may be more generally useful, whereas the Parallella may be better for some kinds of fast Internet server that don't require high bandwidth to storage.  The 10X gigabit advantage of Parallella can of course make a colossal difference under high network load.

Price-wise, the A20 OLinuXino comes in at 55 euro ($71.51) and 65 euro with 4GB onboard Flash ($84.69), versus $99 for 16-core Parallella and $199 for 64-core Parallella, so OLinuXino wins that one easily.  Parallella does have an onboard boot Flash, but it's a tiny 128MB one.

So, swings and roundabouts, and horses for courses.

On applications:

the majority of people just want a cheap media player and don't care what else it might be capable of.  For the 16 or 64 cores to get used they need some practical purpose that's generally useful to more than a demo or niche application.

Adapteva are working on the Pi principle of "give people a cheap board and they'll find the applications".  That's reasonable in itself, but $99 is not cheap, and $199 for the 64-core version even less so.  The "Pi effect" won't kick in at that price, because that kind of money does not fall under the radar for the general population, particularly younger people.  They'll sell a good number (the 6,300 Kickstarter backers make a good start), but my theory is that the sale/price curve is extremely non-linear and only has a huge peak near the origin, then falls off very sharply.  Even the £35 Pi sold above its normal expectations I think because of the unconscious effect of the "$25 computer" advertising which was literally incorrect and partially deceptive for around a year before the Model A appeared.

One application area for Parallella that is mentioned regularly is Software Defined Radio.  It appears that this holds huge interest and has a ready clientelle among the many radio amateurs around the world, quite possibly resulting in thousands of sales all by itself (a bit like XBMC in the case of Pi).  Whether Parallella is useful as a media centre remains to be seen, but that application doesn't justify a $99 expenditure when $35 can do it.

Morgaine.