Parallella $99 board now open hardware on Github

it is perhaps worth noting that although the Parallella board design is open,

the 16-core Epiphany coprocessor's design apparently is not.

The Olimex blog says:

Now everyone can look and learn how this supercomputer was made, the schematic, the board files, the Verilog sources for the FPGA on board all is open and you can view.

but I believe the FPGA they reference refers to the dual-core cpu chip, not the 16-core coprocessor.

coder27 wrote:

 

it is perhaps worth noting that although the Parallella board design is open,

the 16-core Epiphany coprocessor's design apparently is not.

Do you mean that something on the Epiphany device is not documented?  I haven't looked into it at that level.

The HDL for the Zynq's FPGA which interfaces to the Epiphany and HDMI transceiver appears to be available on Github, although I have no idea if what's available is only partial.  I get the feeling from Andreas Olofsson's comments that their intention is that everything relevant be open sourced or open documented.

I don't expect design files for the Epiphany device to be provided, since they're not needed to replicate the board.  End users who develop new versions of the board wouldn't manufacture the Epiphany chip, they would buy them in.  It's no different to buying in an AM335x SoC to make your own open hardware BBB-alike.

Do you mean that something on the Epiphany device is not documented?...

The HDL for the Zynq's FPGA which interfaces to the Epiphany and HDMI transceiver appears to be available on Github

Right.  The HDL is for the Zynq FPGA, not the Epiphany 16-core device where

most of the magic happens. 

It's no different to buying in an AM335x SoC to make your own BBB-alike.

Right.  But the blog wasn't very clear about what was open and what wasn't.

coder27 wrote:

 

Right.  But the blog wasn't very clear about what was open and what wasn't.

I'm not really sure which area harbours doubt in your mind.  There are some issues with Xilinx, but:

Olimex blogged:

 

Now everyone can look and learn how this supercomputer was made, the schematic, the board files, the Verilog sources for the FPGA on board all is open and you can view.

All that seems to be true, subject to checking that the data is complete.  The only FPGA on the board is in the Xilinx Zynq, and they're providing the relevant HDL for that.  I haven't yet seen the low level details of how the Epiphany is programmed and accessed, but if that's fully documented and there are no binary blobs then it does seem that they've produced a genuine open hardware board.

Of course, there's the old Xilinx issue of requiring their proprietary design software if you're going to reprogram the Zynq's FPGA differently, but it shouldn't be needed just for squirting in the bitstream to set the FPGA up for the Parallella board.  And it won't be needed for running Linux on the board.

The only FPGA on the board is in the Xilinx Zynq,

Yes, if you happen to know that the Epiphany isn't an FPGA, then you can deduce

that when they say: "Now everyone can look and learn how this supercomputer was made"

that they aren't referring to the 16-core Epiphany chip.

Ah, fair enough.

Well Epiphany  probably started out being protoyped on FPGAs, maybe just a few cores at a time, but it would be far too slow and also very costly to deliver the end product in FPGAs.  It's not a reconfigurable computer after all, which sometimes do merit end delivery on FPGAs in order to allow their internal structure to be altered.

The Epiphany is a fixed array of special cores, and while I don't know in what semiconductor process it has been manufactured (but it's a fairly modern 28nm one), it's a good bet that it'll be the fastest and cheapest that Adapteva can afford for a device that will be used on a $99 board, which is bound to mean that it's an ASIC like all normal SoCs.

Morgaine Dinova wrote:

 

PS. Note the 4 x Parallella Expansion Connectors (PEC) on the bottom of the board, illustrated on page 19 of the manual and documented on page 26.  They look very flexible for projects, providing access to both Zynq and Epiphany resources.

Oh... I saw 'samtec' and my heart sank.. those look very similar to the ones on the i.MX53-QSB, ridiculously expensive and likely somwhere in the highly difficult to impossible to hand solder category. So likely only useful for projects that have a professionally assembled baseboard that the Parallella can be mounted on.

It's certainly nice to have the expansion available, but I'll take those 2mm headers John likes over these any day

Morgaine Dinova wrote:

 

The 16-core board is priced at US$99 and its host ARM is a dual-core Cortex-A9 (Xilinx Zynq 7010 or 7020).  It comes with 1GB DDR3, host and client USB, native gigabit Ethernet and HDMI, so at that price this would be a fairly interesting board even without its 16-core Epiphany coprocessor. 

I've wondered about these for a while.. 16 or 64 cores of a specialised processor that probably can't run linux or other general purpose OS makes it highly niche.  If they sell many of these, I seriously wonder how many will get used as a dual core Arm with the Ephiphany sitting idle.

Bitcoin miner perhaps ?

selsinork wrote:

 

I've wondered about these for a while.. 16 or 64 cores of a specialised processor that probably can't run linux or other general purpose OS makes it highly niche.  If they sell many of these, I seriously wonder how many will get used as a dual core Arm with the Ephiphany sitting idle.

Kind of like a BBB used for its single-core ARM while its 2 PRUs are sitting idle, except there's 16 of them?

The Epiphany cores seem a lot more capable than PRUs though.  They're clocked at 1GHz, and they each have 1MB of local RAM address space (only partly populated with 32KB per core on the current generation 16 and 64-core devices) as well as slower indirect access to all other cores' memory spaces.

From http://www.adapteva.com/products/silicon-devices/e16g301/ :

 

RISC Processor:
Each compute node contains an independent superscalar floating-point RISC CPU operating at 1 GHz and 2 GFLOPS/sec. The CPU has an efficient general-purpose instruction set that excels at compute intensive applications while being efficiently programmable in C/C++ without any need to write code using assembly or processor specific intrinsics.

Memory System:
The Epiphany memory architecture is based on a flat memory map in which each compute node has a small amount of local memory as a unique addressable slice of the total 32-bit address space. A processor can access its own local memory and other processors memory through regular load/store instructions, with the only difference being the latency and effective throughput of the transactions. The local memory system is comprised of 4 separate banks, allowing for simultaneous memory access by the instruction fetch engine, local load-store instructions, and by load/store transactions initiated by other processors within system.

 

Network-On-Chip:
The eMesh Network-on-Chip is a 2D mesh network that handles all on-chip ad off-chip communication. The network is based on atomic 32- bit memory transactions and is transparent to the program running. The network consists of three separate and orthogonal mesh structures, each serving different types of transaction traffic: one network for on-chip write traffic, one network for off chip write traffic, and one network for all read traffic.

Off-Chip IO:
The eMesh network and memory architecture is extended off-chip using source synchronous LVDS based serial links that provide up to 2GB/sec of effective bandwidth per link. Each E16G301 has 4 links, one in each direction (north, east, west, south), allowing chips to be easily interfaced with FPGAs and/or other E16G301 chips on a board.

I don't know whether the last paragraph means that the Zynq's FPGA has been configured to extend Epiphany core non-local bus access all the way into host memory space.  That would be pretty complex, maybe requiring a split transaction bus or at least some kind of queueing, and of course the contention would be horrible if all cores were to access the host concurrently.  Perhaps there is some kind of core-to-host signaling at least though.

The "4 links, one in each direction (north, east, west, south)" immediately spells "transputer" to us old timers.

Of course, Epiphany cores being programmable in C/C++ is the key feature that will make all the difference in practice.  Here's a video from a year ago demonstrating the same matrix code running on a 64-core Epiphany in 220 ms and on some kind of x86 PC in 4591 ms, while consuming only around 2W.  It suggests that a lot of people are going to like this board.

I'm really looking forward to it becoming generally available.

I wish I had time to play with this board.

I am very intrigued about the processing core.

I was the co-author of a patent application for adaptive algorithms and this core would be a natural for implementing the algorithm for real time use.

sigh,

DAB