AVR Architecture

The AVR Embedded RISC Microcontroller Core is a low-power CMOS 8-bit microprocessor based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, it achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR Core is based on an enhanced RISC architecture that combines a rich instruction set with the 32 general purpose working registers. Each of the 32 registers is directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The architecture supports high level languages efficiently as well as extremely dense assembler code programs. It also provides any number of external and internal interrupts.

The AVR Core is provided in an encrypted netlist format with Verilog and VHDL simulation models, a fully functional test bench and ATPG vectors for >99% fault coverage. It is supported with a full suite of program and system development tools including: macro assemblers, ANSI C Compilers, program debugger/simulators, and in-circuit emulator.

Features

Utilizes the AVR Enhanced RISC Architecture
- High Performance and Low Power
- Sleep Mode to Conserve Power
120 Powerful Instructions - Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Operating Range: 1.6 to 3.6 Volts
Fully Static Operation, 0-33 MHz (0.5 micron), 0-45 MHz (0.35 micron)
Seven External Interrupt Sources
AVR Scalable Test Access Interface
Test Vectors for >99% Fault Coverage
Verilog and VHDL Simulation Models
Faster Version can be Created Upon Request

Enhancing Access with Working Registers

Usually, when the CPU executes a program, it requires frequent access to a limited set of data, including pointers, loop counters, semaphore status bits, and array indexes. In fact, close inspection of source code will reveal that most of the data is only required for a very short amount of time, then later discarded. That is why the AVR CPU contains multiple "working registers," which store dynamic data inside the CPU. Organized in a "register file," they eliminate the need to move temporary data from CPU to SRAM—only to read it back a few cycles later. The register file is extremely fast, allowing the CPU to read, execute, and store the result back into a register in a single clock cycle. They also require far less energy when accessed, compared to accessing a large SRAM with long address and data lines. Because no cycles are wasted, power consumption for executing code is greatly reduced.

DSP Instructions

The 32-bit AVR contains a very wide instruction set—with integer, fixed point and floating point DSP instructions—giving it the highest CPU performance of any AVR CPU. The 32-bit AVR instruction set includes saturation and rounding instructions that help speed up loops by requiring no internal range check of intermediate results. With fast multiply, accumulate, and divide instructions, the 32-bit AVR is the perfect choice for applications that require extensive digital signal processing.