Freescale: ColdFire V2 Family Overview

ColdFire V2  Architectural Features:

• Variable-length RISC, clock multiplied core
• Independent, decoupled pipelines Two-stage instruction fetch pipeline (IFP) Two-stage operand execution pipeline (OEP) FIFO instruction buffer is the decoupling mechanism
• 16 user-accessible, 32-bit wide general purpose registers
• 32-bit data bus
• 32-bit address bus supporting a 4 Gigabyte linear addressing range
• Sophisticated two-level branch acceleration mechanisms minimize change-of-flow execution time
• Background debug module (BDM), real-time trace (RTT) and real-time debug (RTD) support
• Binary object code compatibility across the entire 68K/ColdFire family
• Enhanced multiply-accumulate (EMAC) execute engine provides high-speed signal processing capabilities with four 40-bit accumulators and single-cycle instruction issue rate on 32 x 32 +_ 32 MAC operations
• Vector base register to relocate the exception-vector table
• 100 percent synthesizable and technology-independent designs
• Implementation
  • Fully synthesizable, retargetable core
  • 166 MHz, 160 Dhry 2.1 MIPS (0.13 um)
  • ~50k gates for V2 core only

Standard Product Platform–SPP features:

• V2 ColdFire core—100–160 MHz
• EMAC module, HW divide
• AXBS (multi AHB crossbar switch) connects multiple masters with various slave IP blocks
• External bus interface (16- or 32-bit)
• DFT emphasis for SoC functional fault coverage and test
• Muxed DFF rising-edge clocked design
• Static timing analysis
• Range of cache and local memory sizes, pipeline options
• Integrated peripherals 10/100 Fast Ethernet controller with DMA QSPI I2C Three UARTs DMA Chip selects, general-purpose I/Os Four 32-bit timers World-class background debug module