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Re: WHY theses DRC errors?

Former Member

On 1/6/2012 3:21 PM, alah wrote:

  Hi, everybody. I drew my schematic and built my board. It LOOKs very fine even on a print but when I run DRC I get CLEARENCE and OVERLAP errors; WHY?

Oops, now another question; Why can´t we attatch eagle files? Thanks, Alberto.

 

 

The clearance errors are determined by what is set in the drc settings

clearance tab. Either it set set too small or traces are too close together.

 

Overlap is exactly that, two nets are touching. This can happen on some

homemade library parts with unconnected copper (custom pad shape, etc

)on the pads. Double click on the errors on the box and it should become

clear what is happening.

 

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  • alah wrote:

    ............ Why can´t we attatch eagle

    files? Thanks, Alberto.

     

    Likely because they are to large. You need to keep them smaller than about

    46k for them to be accepted and make it to all the nodes that access these

    forums. You should zip them if they are to large.

    Also its nice if you state which version they were generated in

     

    HTH

    Warren

     

     

    --

    Viewed / responded via the newsgroup at

    news.cadsoft.de

     

     

     

Reply

  • alah wrote:

    ............ Why can´t we attatch eagle

    files? Thanks, Alberto.

     

    Likely because they are to large. You need to keep them smaller than about

    46k for them to be accepted and make it to all the nodes that access these

    forums. You should zip them if they are to large.

    Also its nice if you state which version they were generated in

     

    HTH

    Warren

     

     

    --

    Viewed / responded via the newsgroup at

    news.cadsoft.de

     

     

     

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