Re: WHY theses DRC errors?

On 1/6/2012 3:21 PM, alah wrote:

  Hi, everybody. I drew my schematic and built my board. It LOOKs very fine even on a print but when I run DRC I get CLEARENCE and OVERLAP errors; WHY?

Oops, now another question; Why can´t we attatch eagle files? Thanks, Alberto.

 

The clearance errors are determined by what is set in the drc settings

clearance tab. Either it set set too small or traces are too close together.

Overlap is exactly that, two nets are touching. This can happen on some

homemade library parts with unconnected copper (custom pad shape, etc

)on the pads. Double click on the errors on the box and it should become

clear what is happening.

alah wrote:

............ Why can´t we attatch eagle

files? Thanks, Alberto.

Likely because they are to large. You need to keep them smaller than about

46k for them to be accepted and make it to all the nodes that access these

forums. You should zip them if they are to large.

Also its nice if you state which version they were generated in

HTH

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de

OK Doug; I knew I had three of these errors on just one pad, so I deleted the trace and observed that there was still a dot of red on the pad. So I moved it and it stretched out of the pad and I knew that is because I use a too fine gridand maybe the mouse moves or  whatever. I rerouted and that solved three errors.

I still have two and I can´t find an explanation; hope You can:

I have a TO220V  transistor with three pads in line. The middle and right pads were indicating overlap. The left pad has a left route, the middle pad has a down route and the right pad has a down route, parallel to the middle route. I deleted the right route and the right error was gone but not the middle. Even though my route is completed I can see a tiny line of UNrouted on the pad, which I managed to delete. NO errors now so guess that I´m using TOO fine a grid: 0.1mm. What do You think? Thanks.

I hope I´m responding to Warren. I doubt it´s that large.It´s only 36 x 42 mm; 1 TO220V, 4 -10 diodes, three caps and 4 V Rs.I´ll try again, Thanks.

On 1/6/2012 6:01 PM, alah wrote:

OK Doug; I knew I had three of these errors on just one pad, so I deleted the trace and observed that there was still a dot of red on the pad. So I moved it and it stretched out of the pad and I knew that is because I use a too fine gridand maybe the mouse moves or  whatever. I rerouted and that solved three errors.

I still have two and I can´t find an explanation; hope You can:

I have a TO220V  transistor with three pads in line. The middle and right pads were indicating overlap. The left pad has a left route, the middle pad has a down route and the right pad has a down route, parallel to the middle route. I deleted the right route and the right error was gone but not the middle. Even though my route is completed I can see a tiny line of UNrouted on the pad, which I managed to delete. NO errors now so guess that I´m using TOO fine a grid: 0.1mm. What do You think? Thanks.

 

I do not think that the problem is the fineness of the grid because an

overlap indicates that two (or more) nets are contacting whereas if you

had missed the pad (it should snap) it would merely be an airwire.

I suspect stray copper.