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EAGLE User Chat (English) 6.1.5, DRC err on tStop layer...sometimes
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6.1.5, DRC err on tStop layer...sometimes

e14 Contributor
e14 Contributor over 14 years ago

Hi,

 

Most likely my error someplace, brand new to Eagle CAD. Anyway, my

question is: Is tStop layer invisible by default? Reason for this

question: I was down to zero DRC errors on my first small board layout

with Eagle, then I notice part of the perimeter (layer 20) had vanished

on my layout. So, I turned off view of all layers, then turned on just

layer 20 so I could redraw the border outline. Fine, done with that,

turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

How is it possible to not see this before? Just for fun, I turned off

tStop layer and ran DRC again. No errors! What the heck... can anyone

shed some light on this, is there something I need to fix? By the way, I

did 99% of this layout with original default design rules, then found

that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

see errors before turning on ALL layers. Should I be concerned about

these errors I almost did not notice before ordering boards? I made

Gerber files & looked at them with GerbV, they look fine to my

eyeball...but i don't perceive 3mil objects all that well! That seems to

be the top solder mask min/max in the SunStone rules.

 

Thanks for any enlightenment,

Bill

 

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  • e14 Contributor
    e14 Contributor over 14 years ago

    Am 13.04.2012 05:51, schrieb Bill Martin:

    Hi,

     

    Most likely my error someplace, brand new to Eagle CAD. Anyway, my

    question is: Is tStop layer invisible by default? Reason for this

    question: I was down to zero DRC errors on my first small board layout

    with Eagle, then I notice part of the perimeter (layer 20) had vanished

    on my layout. So, I turned off view of all layers, then turned on just

    layer 20 so I could redraw the border outline. Fine, done with that,

    turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

    How is it possible to not see this before? Just for fun, I turned off

    tStop layer and ran DRC again. No errors! What the heck... can anyone

    shed some light on this, is there something I need to fix? By the way, I

    did 99% of this layout with original default design rules, then found

    that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

    see errors before turning on ALL layers. Should I be concerned about

    these errors I almost did not notice before ordering boards? I made

    Gerber files & looked at them with GerbV, they look fine to my

    eyeball...but i don't perceive 3mil objects all that well! That seems to

    be the top solder mask min/max in the SunStone rules.

     

    Thanks for any enlightenment,

    Bill

     

    DRC checks visible (selected) layers only.

     

    --

    Mit freundlichen Grüßen / With best regards

     

    Joern Paschedag

     

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  • e14 Contributor
    e14 Contributor over 14 years ago

    Am 13.04.2012 05:51, schrieb Bill Martin:

    Hi,

     

    Most likely my error someplace, brand new to Eagle CAD. Anyway, my

    question is: Is tStop layer invisible by default? Reason for this

    question: I was down to zero DRC errors on my first small board layout

    with Eagle, then I notice part of the perimeter (layer 20) had vanished

    on my layout. So, I turned off view of all layers, then turned on just

    layer 20 so I could redraw the border outline. Fine, done with that,

    turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

    How is it possible to not see this before? Just for fun, I turned off

    tStop layer and ran DRC again. No errors! What the heck... can anyone

    shed some light on this, is there something I need to fix? By the way, I

    did 99% of this layout with original default design rules, then found

    that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

    see errors before turning on ALL layers. Should I be concerned about

    these errors I almost did not notice before ordering boards? I made

    Gerber files & looked at them with GerbV, they look fine to my

    eyeball...but i don't perceive 3mil objects all that well! That seems to

    be the top solder mask min/max in the SunStone rules.

     

    Thanks for any enlightenment,

    Bill

     

    DRC checks visible (selected) layers only.

     

    --

    Mit freundlichen Grüßen / With best regards

     

    Joern Paschedag

     

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
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