6.1.5, DRC err on tStop layer...sometimes

On 04/13/2012 08:31 AM, Robert Scott wrote:

On Thu, 12 Apr 2012 20:51:25 -0700, Bill Martin<wwm@wwmartin.net>

wrote:

 

>> Hi,

>>

I just posted a similar issue in the support forum and got the same

answer as you got from Joern.  DRC only checks visible layers.  I also

got lots of tStop errors when I temporarily turned on tStop (29)

visibility.  It turned out that all those errors were for the

silkscreen layer overlapping the stop mask.  However even those errors

seemed to be calculated on unrealistic rules.  It seems that a

conflict is detected when any part of the silkscreen text rectangle

intersects with any part of the stop mask, even if no part of the

actual silkscreen text is anywhere near the stop mask.  I suppose it

is just very difficult for Eagle to check the rendering of each letter

in the text to see if it overlaps with the stop mask.  It is much

easier to just check the rectangle that contains the text.  In most

cases you can just approve such errors and go on.  But imagine what

would happen if some silkscreen were placed squarely on top of a

surface-mount pad.  It would make that pad unsolderable.  So we

certainly want an error to be declared in that case.

 

Robert Scott

Ypsilanti, Michigan

Ok, it seems like the majority of my 31 DRC errors came from a couple of

thru-hole library parts I used. The rest appear to be of the

"encroaching text rectangle" variety, so I think I am done with this

little exercise.

It certainly is great to have these newsgroups for sanity checking!

Bill

Bill Martin wrote:

.................. I have not found any way to make these tStop errors

go away, short of just turning off visibility to layer 29. This does

not seem normal...or correct. Maybe the thing to do is just submit

the files to SunStone & see if "their" DRC passes or fails.

 

Best Regards,

Bill

One of the most usefull and common actions a  board house will do is post

process your design to remove any silk sreen that is not on top of solder

solder mask.

As always you need to confirm your chosen board house does this.

Generally it is accepted that you should have your libraries as correct as

possible in this matter. Names that are smashed and moved later should be

placed sensibly to prevent placement in mask clear areas. The board house

then chops out the remainder

HTH

Warren

--

Viewed / responded via the newsgroup at

news.cadsoft.de

On 4/13/2012 11:31 AM, Robert Scott wrote:

On Thu, 12 Apr 2012 20:51:25 -0700, Bill Martin<wwm@wwmartin.net>

wrote:

 

>> Hi,

>>

>> Most likely my error someplace, brand new to Eagle CAD. Anyway, my

>> question is: Is tStop layer invisible by default? Reason for this

>> question: I was down to zero DRC errors on my first small board layout

>> with Eagle, then I notice part of the perimeter (layer 20) had vanished

>> on my layout. So, I turned off view of all layers, then turned on just

>> layer 20 so I could redraw the border outline. Fine, done with that,

>> turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

>> How is it possible to not see this before? Just for fun, I turned off

>> tStop layer and ran DRC again. No errors! What the heck... can anyone

>> shed some light on this, is there something I need to fix? By the way, I

>> did 99% of this layout with original default design rules, then found

>> that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

>> see errors before turning on ALL layers. Should I be concerned about

>> these errors I almost did not notice before ordering boards? I made

>> Gerber files&  looked at them with GerbV, they look fine to my

>> eyeball...but i don't perceive 3mil objects all that well! That seems to

>> be the top solder mask min/max in the SunStone rules.

 

I just posted a similar issue in the support forum and got the same

answer as you got from Joern.  DRC only checks visible layers.  I also

got lots of tStop errors when I temporarily turned on tStop (29)

visibility.  It turned out that all those errors were for the

silkscreen layer overlapping the stop mask.  However even those errors

seemed to be calculated on unrealistic rules.  It seems that a

conflict is detected when any part of the silkscreen text rectangle

intersects with any part of the stop mask, even if no part of the

actual silkscreen text is anywhere near the stop mask.  I suppose it

is just very difficult for Eagle to check the rendering of each letter

in the text to see if it overlaps with the stop mask.  It is much

easier to just check the rectangle that contains the text.  In most

cases you can just approve such errors and go on.  But imagine what

would happen if some silkscreen were placed squarely on top of a

surface-mount pad.  It would make that pad unsolderable.  So we

certainly want an error to be declared in that case.

 

Robert Scott

Ypsilanti, Michigan

On 04/13/2012 01:10 AM, Joern Paschedag wrote:

Am 13.04.2012 05:51, schrieb Bill Martin:

>> Hi,

>>

>> Most likely my error someplace, brand new to Eagle CAD. Anyway, my

>> question is: Is tStop layer invisible by default? Reason for this

>> question: I was down to zero DRC errors on my first small board layout

>> with Eagle, then I notice part of the perimeter (layer 20) had vanished

>> on my layout. So, I turned off view of all layers, then turned on just

>> layer 20 so I could redraw the border outline. Fine, done with that,

>> turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

>> How is it possible to not see this before? Just for fun, I turned off

>> tStop layer and ran DRC again. No errors! What the heck... can anyone

>> shed some light on this, is there something I need to fix? By the way, I

>> did 99% of this layout with original default design rules, then found

>> that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

>> see errors before turning on ALL layers. Should I be concerned about

>> these errors I almost did not notice before ordering boards? I made

>> Gerber files & looked at them with GerbV, they look fine to my

>> eyeball...but i don't perceive 3mil objects all that well! That seems to

>> be the top solder mask min/max in the SunStone rules.

>>

>> Thanks for any enlightenment,

>> Bill

 

DRC checks visible (selected) layers only.

 

Ok, thank you for the confirmation of my "discovery". This then implies

that the tStop layer is by default not visible. Is the the correct

behavior? I have not found any way to make these tStop errors go away,

short of just turning off visibility to layer 29. This does not seem

normal...or correct. Maybe the thing to do is just submit the files to

SunStone & see if "their" DRC passes or fails.

Best Regards,

Bill

On Thu, 12 Apr 2012 20:51:25 -0700, Bill Martin <wwm@wwmartin.net>

wrote:

>Hi,

>Most likely my error someplace, brand new to Eagle CAD. Anyway, my

>question is: Is tStop layer invisible by default? Reason for this

>question: I was down to zero DRC errors on my first small board layout

>with Eagle, then I notice part of the perimeter (layer 20) had vanished

>on my layout. So, I turned off view of all layers, then turned on just

>layer 20 so I could redraw the border outline. Fine, done with that,

>turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

>How is it possible to not see this before? Just for fun, I turned off

>tStop layer and ran DRC again. No errors! What the heck... can anyone

>shed some light on this, is there something I need to fix? By the way, I

>did 99% of this layout with original default design rules, then found

>that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

>see errors before turning on ALL layers. Should I be concerned about

>these errors I almost did not notice before ordering boards? I made

>Gerber files & looked at them with GerbV, they look fine to my

>eyeball...but i don't perceive 3mil objects all that well! That seems to

>be the top solder mask min/max in the SunStone rules.

I just posted a similar issue in the support forum and got the same

answer as you got from Joern.  DRC only checks visible layers.  I also

got lots of tStop errors when I temporarily turned on tStop (29)

visibility.  It turned out that all those errors were for the

silkscreen layer overlapping the stop mask.  However even those errors

seemed to be calculated on unrealistic rules.  It seems that a

conflict is detected when any part of the silkscreen text rectangle

intersects with any part of the stop mask, even if no part of the

actual silkscreen text is anywhere near the stop mask.  I suppose it

is just very difficult for Eagle to check the rendering of each letter

in the text to see if it overlaps with the stop mask.  It is much

easier to just check the rectangle that contains the text.  In most

cases you can just approve such errors and go on.  But imagine what

would happen if some silkscreen were placed squarely on top of a

surface-mount pad.  It would make that pad unsolderable.  So we

certainly want an error to be declared in that case.

Robert Scott

Ypsilanti, Michigan

Am 13.04.2012 05:51, schrieb Bill Martin:

Hi,

 

Most likely my error someplace, brand new to Eagle CAD. Anyway, my

question is: Is tStop layer invisible by default? Reason for this

question: I was down to zero DRC errors on my first small board layout

with Eagle, then I notice part of the perimeter (layer 20) had vanished

on my layout. So, I turned off view of all layers, then turned on just

layer 20 so I could redraw the border outline. Fine, done with that,

turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

How is it possible to not see this before? Just for fun, I turned off

tStop layer and ran DRC again. No errors! What the heck... can anyone

shed some light on this, is there something I need to fix? By the way, I

did 99% of this layout with original default design rules, then found

that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

see errors before turning on ALL layers. Should I be concerned about

these errors I almost did not notice before ordering boards? I made

Gerber files & looked at them with GerbV, they look fine to my

eyeball...but i don't perceive 3mil objects all that well! That seems to

be the top solder mask min/max in the SunStone rules.

 

Thanks for any enlightenment,

Bill

DRC checks visible (selected) layers only.

--

Mit freundlichen Grüßen / With best regards

Joern Paschedag