6.1.5, DRC err on tStop layer...sometimes

On 04/13/2012 01:10 AM, Joern Paschedag wrote:

Am 13.04.2012 05:51, schrieb Bill Martin:

>> Hi,

>>

>> Most likely my error someplace, brand new to Eagle CAD. Anyway, my

>> question is: Is tStop layer invisible by default? Reason for this

>> question: I was down to zero DRC errors on my first small board layout

>> with Eagle, then I notice part of the perimeter (layer 20) had vanished

>> on my layout. So, I turned off view of all layers, then turned on just

>> layer 20 so I could redraw the border outline. Fine, done with that,

>> turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

>> How is it possible to not see this before? Just for fun, I turned off

>> tStop layer and ran DRC again. No errors! What the heck... can anyone

>> shed some light on this, is there something I need to fix? By the way, I

>> did 99% of this layout with original default design rules, then found

>> that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

>> see errors before turning on ALL layers. Should I be concerned about

>> these errors I almost did not notice before ordering boards? I made

>> Gerber files & looked at them with GerbV, they look fine to my

>> eyeball...but i don't perceive 3mil objects all that well! That seems to

>> be the top solder mask min/max in the SunStone rules.

>>

>> Thanks for any enlightenment,

>> Bill

 

DRC checks visible (selected) layers only.

 

Ok, thank you for the confirmation of my "discovery". This then implies

that the tStop layer is by default not visible. Is the the correct

behavior? I have not found any way to make these tStop errors go away,

short of just turning off visibility to layer 29. This does not seem

normal...or correct. Maybe the thing to do is just submit the files to

SunStone & see if "their" DRC passes or fails.

Best Regards,

Bill

On 04/13/2012 01:10 AM, Joern Paschedag wrote:

Am 13.04.2012 05:51, schrieb Bill Martin:

>> Hi,

>>

>> Most likely my error someplace, brand new to Eagle CAD. Anyway, my

>> question is: Is tStop layer invisible by default? Reason for this

>> question: I was down to zero DRC errors on my first small board layout

>> with Eagle, then I notice part of the perimeter (layer 20) had vanished

>> on my layout. So, I turned off view of all layers, then turned on just

>> layer 20 so I could redraw the border outline. Fine, done with that,

>> turn on ALL layers and ran DRC. Now have about 30 errors re tStop layer.

>> How is it possible to not see this before? Just for fun, I turned off

>> tStop layer and ran DRC again. No errors! What the heck... can anyone

>> shed some light on this, is there something I need to fix? By the way, I

>> did 99% of this layout with original default design rules, then found

>> that SunStone had a .DRU file for Eagle, so I loaded that. Still did not

>> see errors before turning on ALL layers. Should I be concerned about

>> these errors I almost did not notice before ordering boards? I made

>> Gerber files & looked at them with GerbV, they look fine to my

>> eyeball...but i don't perceive 3mil objects all that well! That seems to

>> be the top solder mask min/max in the SunStone rules.

>>

>> Thanks for any enlightenment,

>> Bill

 

DRC checks visible (selected) layers only.

 

Ok, thank you for the confirmation of my "discovery". This then implies

that the tStop layer is by default not visible. Is the the correct

behavior? I have not found any way to make these tStop errors go away,

short of just turning off visibility to layer 29. This does not seem

normal...or correct. Maybe the thing to do is just submit the files to

SunStone & see if "their" DRC passes or fails.

Best Regards,

Bill